New Verilog-2001 Techniques for Creating …

HDLCON 20021 New Verilog-2001 Techniques for Creating Parameterized ModelsRev (or Down With `define and Death of a defparam!)New Verilog-2001 Techniques for Creating Parameterized Models(or Down With `define and Death of a defparam!)Clifford E. CummingsSunburst Design, reusable models typically requires thatgeneral-purpose models be written with re-definableparameters such as SIZE, WIDTH and respect to coding parameterized verilog models,two verilog constructs that are over-used and abused arethe global macro definition (`define) and the infinitelyabusable parameter redefinition statement (defparam).This paper will detail Techniques for coding properparameterized models, detail the differences betweenparameters and macro definitions, present guidelines forusing macros, parameters and parameter definitions,discourage the use of defparams, and detail verilog -2001enhancements to enhance coding and usage ofparameterized IntroductionTwo verilog constructs that are overused and abusedare the verilog macro definition statement (`define) andthe infinitely abusable defparam statement.

HDLCON 2002 1 New Verilog-2001 Techniques for Creating Parameterized Models Rev 1.2 (or Down With `define and Death of a defparam!) New Verilog-2001 Techniques for Creating Parameterized Models

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