Simulation and Synthesis Techniques for …

Expert Verilog, SystemVerilog & Synthesis TrainingSimulation and Synthesis Techniques for AsynchronousFIFO DesignClifford E. Cummings, Sunburst Design, are often used to safely pass data from one clock domain to another asynchronous clock domain. Using aFIFO to pass data from one clock domain to another clock domain requires multi- asynchronous clock designtechniques. There are many ways to design a fifo wrong. There are many ways to design a fifo right but stillmake it difficult to properly synthesize and analyze the paper will detail one method that is used to design, synthesize and analyze a safe fifo between different clockdomains using Gray code pointers that are synchronized into a different clock domain before testing for " fifo full"or " fifo empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model ( fifo Style #1) Editorial CommentA second fifo paper by the same author was voted Best Paper - 1st Place by SNUG attendees, is listed asreference [3] and is also available for San Jose 2002 Simulation and Synthesis Techniques forRev fifo IntroductionAn asynchronous fifo refers to a fifo design where data values are written to a fifo buffer from one clockdomain and the data values are read from the same fifo buffer from another clock domain, where the two clockdomains are asynchronous to each FIFOs are used to safely pass data from one clo

Expert Verilog, SystemVerilog & Synthesis Training Simulation and Synthesis Techniques for Asynchronous FIFO Design Clifford E. Cummings, Sunburst Design, Inc. cliffc@sunburst-design.com

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