Transcription of Parallel Lapping of Semiconductor Devices for …
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Parallel Lapping of Semiconductor Devices for …
Page 1 of 5 1120 Via Callejon San Clemente, CA 92673 USA Voice: Fax: Sales: Email: Visit us at: : Purpose Parallel Lapping is a commonly used process in failure analysis, debug, and general construction analysis in the production of integrated circuits. In many cases it is necessary to remove layers from the integrated circuit for inspection, whether it be electrical testing, deposition uniformity, or device integrity investigation. The precise removal of these layers requires accuracy, knowledge of components and materials systems, and equipment capable of implementing precision polishing techniques. Parallel Lapping (often called delayering ) is useful to remove specific device layers when evaluating the design of any device or for specific failure analysis techniques. Equipment used for this type of specimen preparation must be adaptable to many different materials such as Nitrides, Oxides, Aluminum, and for current Devices Copper and low dielectric constant materials.
57.DOC 1120 Via Callejon • San Clemente, CA 92673 USA Page 3 of 5 Voice: 949.492.2600 • Fax: 949.492.1499 • Sales: 800.728.2233 Email: sbt@southbaytech.com • Visit us at: www.southbaytech.com
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