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The RISC-V Processor

The RISC-V ProcessorHakim WeatherspoonCS 3410 Computer ScienceCornell University[Weatherspoon, Bala, Bracy, and Sirer]2 AnnouncementsCheck online syllabus/schedule Slides and Reading for lectures Office Hours Pictures of all TAs Dates to keep in Mind Prelims: Tue Mar 5th and Thur May 2nd Proj 1: Due next Friday, Feb 15th Proj3: Due before Spring break Final Project: Due when final will be Feb 16thSchedule is subject to change3 Collaboration, Late, Re-grading Policies White Board Collaboration Policy Can discuss approach together on a white board Leave, watch a movie such as Stranger Things, then write up solution independently Do not copy solutionsLate Policy Each person has a total of four slip days Max of twoslip days for any individual assignment Slip days deducted first for anylate assignment, cannot selectively apply slip days For projects.

ARISC-V CPU with a (modified) Harvard architecture ... Fetch Decode Execute Memory WB A single cycle processor –this diagram is not 100% spatial. Basic CPU execution loop 1. Instruction Fetch 2. Instruction Decode 3. Execution (ALU) 4. Memory Access 5. Register Writeback

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