The RISC-V Processor

1 The RISC-V ProcessorHakim WeatherspoonCS 3410 Computer ScienceCornell University[Weatherspoon, Bala, Bracy, and Sirer]2 AnnouncementsCheck online syllabus/schedule Slides and Reading for lectures Office Hours Pictures of all TAs Dates to keep in Mind Prelims: Tue Mar 5th and Thur May 2nd Proj 1: Due next Friday, Feb 15th Proj3: Due before Spring break Final Project: Due when final will be Feb 16thSchedule is subject to change3 Collaboration, Late, Re-grading Policies White Board Collaboration Policy Can discuss approach together on a white board Leave, watch a movie such as Stranger Things, then write up solution independently Do not copy solutionsLate Policy Each person has a total of four slip days Max of twoslip days for any individual assignment Slip days deducted first for anylate assignment, cannot selectively apply slip days For projects.

2 Slip days are deducted from all partners 25%deducted per day late after slip days are exhaustedRegrade policy Submit written request within a week of receiving score4 Big Picture: Building a ProcessorPCimmmemorytargetoffsetcmpcontr ol=?new pcmemorydindoutaddrregisterfileinstexten dA single cycle processoralu+4+45 Goal for the next 2 lectures Understanding the basics of a Processor We now have the technology to build a CPU! Putting it all together: Arithmetic Logic Unit (ALU) Register File Memory- SRAM: cache- DRAM: main memory RISC-V Instructions & how they are executed56 PCimmmemorytargetoffsetcmpcontrol=?

3 New pcmemorydindoutaddrregisterfileinstexten daluRISC-VRegister File+4+4A single cycle processor7 RISC-VRegister File RISC-V register file 32 registers, 32-bits each x0 wired to zero Write port indexed via RW- on falling edge when WE=1 Read ports indexed via RA, RBDual-Read-PortSingle-Write-Port32 x 32 Register FileQAQBDWRWRARBWE3232321555 RISC-VRegister File RISC-V register file 32 registers, 32-bits each x0 wired to zero Write port indexed via RW- on falling edge when WE=1 Read ports indexed via RA, RB RISC-V register file Numbered from 0 to 31 Can be referred by number: x0, x1, x2.

4 X31 Convention, each register also has a name: - x10 x17 a0 a7, x28 x31 t3 QuestionIf we wanted to support 64 registers, what would change?a) W, A, B 64b) RW, RA, RB5 6c) W 32 64, RW5 6d) A & B QuestionIf we wanted to support 64 registers, what would change?a) W, A, B 64b) RW, RA, RB5 6c) W 32 64, RW5 6d) A & B pcmemorydindoutaddrregisterfileinstexten daluRISC-VMemory+4+4A single cycle processor12 RISC-VMemory 32-bit address 32-bit data (but byte addressed) Enable + 2 bit memory control (mc)00: read word (4 byte aligned)01: write byte10: write halfword (2 byte aligned)11: write word (4 byte aligned)memory32addr2mc3232 EDinDout0x000fffff.

5 0x0000000b0x0000000a0x000000090x00000008 0x000000070x000000060x000000050x00000004 0x000000030x000000020x000000010x00000000 0x051 byteaddress13 PCimmmemorytargetoffsetcmpcontrol=?new pcmemorydindoutaddrregisterfileinstexten daluPutting it all together: Basic Processor +4+4A single cycle processorNeed a program Stored program computerArchitectures von Neumann architecture Harvard (modified) architectureTo make a computer14 Need a program Stored program computer (a Universal Turing Machine)Architectures von Neumann architecture Harvard (modified) architectureTo make a computer1516A RISC-V CPU with a (modified) Harvard architecture Modified.

6 Instructions & data in common address space, separate instr/data caches can be accessed in parallelCPUR egistersDataMemorydata, address, it all together: Basic Processor17A Processor executes instructions Processor has some internal state in storage elements (registers)A memory holds instructions and data (modified) Harvard architecture : separate insts and data von Neumann architecture : combined inst and dataA bus connects the twoWe now have enough building blocks to build machines that can perform non-trivial computational tasksTakeawayNext Goal18 How to program and execute instructions on a RISC-V Processor ?

7 Instructions are stored in memory, encoded in binaryA basic Processor fetches decodes executesone instruction at a timeInstruction Usage19pcaddercur instdecoderegsexecuteaddrdata00000000101 0000100000000000100110010000000000001000 0000000010000000000000010001000011000001 0101010 x2 x0 op=addi20 Instruction ProcessingA basic Processor fetches decodes executesone instruction at a +4 DataMemInstructions: stored in memory, encoded in binaryLevels of Interpretation: Instructions21 High Level Language C, Java, Python, ADA, .. Loops, control flow, variablesfor (i = 0; i < 10; i++)printf( go cucs );main: addi x2, x0, 10addi x1, x0, 0loop: slt x3, x1, Language No symbols (except labels) One operation per statement human readable machine language Machine Language Binary-encoded assembly Labels become addresses The language of the CPUALU, Control, Register File.

8 Machine Implementation(Microarchitecture)Instruc tion Set Architecture0000000010100001000000000001 0011001000000000000100000000000100000000 000000100010000110000010101010 x2 x0 op=addiDifferent CPU architectures specify different instructionsTwo classes of ISAs Reduced Instruction Set Computers (RISC)IBM Power PC, Sun Sparc, MIPS, Alpha Complex Instruction Set Computers (CISC)Intel x86, PDP-11, VAXA nother ISA classification: Load/Store architecture Data must be in registers to be operated onFor example: array[x] = array[y] + array[z]1 add ? OR 2 loads, an add, and a store ?

9 Keeps HW simple many RISC ISAs are load/storeInstruction Set architecture (ISA)2223iClicker QuestionWhat does it mean for an architecture to be called a load/store architecture ?(A)Load and Store instructions are supported by the ISA.(B)Load and Store instructions can also perform arithmetic instructions on data in memory.(C)Data must first be loaded into a register before it can be operated on.(D)Every load must have an accompanying store at some later point in the QuestionWhat does it mean for an architecture to be called a load/store architecture ?(A)Load and Store instructions are supported by the ISA.

10 (B)Load and Store instructions can also perform arithmetic instructions on data in memory.(C)Data must first be loaded into a register before it can be operated on.(D)Every load must have an accompanying store at some later point in the RISC-V Processor and ISA (instruction set architecture ) is an example a Reduced Instruction Set Computers (RISC) where simplicity is key, thus enabling us to build it!!Next Goal26 How are instructions executed? What is the general datapath to execute an instruction?Five Stages of RISC-V +4 DataMemFetchDecodeExecuteMemoryWBA single cycle Processor this diagram is not 100% spatialBasic CPU execution loop1.