PDF4PRO ⚡AMP

Modern search engine that looking for books and documents around the web

Example: biology

Computer Architecture: Vector Processing: …

Computer Architecture: SIMD/ Vector /GPUProf. Onur Mutlu (edited by seth)Carnegie Mellon UniversityVector Processing: Exploiting Regular (Data) ParallelismData Parallelism Concurrency arises from performing the same operations on different pieces of data Single instruction multiple data (SIMD) , dot product of two vectors Contrast with data flow Concurrency arises from executing different operations in parallel (in a data driven manner) Contrast with thread ( control ) parallelism Concurrency arises from executing different threads of control in parallel SIMD exploits instruction-level parallelism Multiple instructions concurrent: instructions happen to be the same 3 SIMD Processing Single instruction operates on multiple data elements In time or in space Multiple processing elements Time-space duality Array processor: Instruction operates on multiple data elements at the same time Vector processor: Instruction operates on multiple data elements in consecutive time steps4 Arr

Example: 16 banks; can start one bank access per cycle Bank latency: 11 cycles Can sustain 16 parallel accesses if they go to different banks 16 Bank 0 Bank 1 MDR MAR Bank 2 Bank 15 MDR MAR MDR MAR MDR MAR Data bus Address bus CPU Slide credit: Derek Chiou

Fullscreen Download
Loading..

Tags:

  Architecture, Cycle, Vector

Information

Domain:

Source:

Link to this page:

Please notify us if you found a problem with this document:

Spam in document Broken preview Other abuse

Transcription of Computer Architecture: Vector Processing: …

Documents from same domain

Computer Architecture: Multithreading

course.ece.cmu.edu

Sun Niagara Multithreaded Pipeline 13 Tera MTA Fine-grained Multithreading 256 processors, each with a 21-cycle pipeline 128 active threads A thread can issue instructions every 21 cycles Then, why 128 threads? Memory latency: approximately 150 cycles No data cache Threads can be blocked waiting for memory More threads better ability to tolerate memory latency

  Multithreading

Computer Architecture: Branch Prediction

course.ece.cmu.edu

How to Handle Control Dependences Critical to keep the pipeline full with correct sequence of dynamic instructions. Potential solutions if the instruction is a control-flow instruction: Stall the pipeline until we know the next fetch address Guess the next fetch address (branch prediction) Employ delayed branching (branch delay slot) Do something else (fine-grained multithreading)

  Architecture, Prediction, Branch, Branch prediction

Computer Architecture: Dataflow (Part I)

course.ece.cmu.edu

Computer Architecture,” ACM Computing Surveys 1982. ! Veen, “Dataflow Machine Architecture,” ACM Computing Surveys 1986. ! Gurd et al., “The Manchester prototype dataflow computer,” CACM 1985. ! Arvind and Nikhil, “Executing a Program on the MIT Tagged-Token Dataflow Architecture,” IEEE TC 1990. !

  Architecture, Computer, Computer architecture, Dataflow, Dataflow computer, Dataflow architecture

Computer Architecture: Main Memory (Part I)

course.ece.cmu.edu

Memory Bank Organization and Operation Read access sequence: 1. Decode row address & drive word-lines 2. Selected bits drive bit-lines • Entire row read 3. Amplify row data 4. Decode column address & select subset of row • Send to output 5. …

  Memory, Computer, Organization

CMOS Power Consumption - ECE:Course Page

course.ece.cmu.edu

Ways to reducing power consumption Load capacitance (C L) ⌧Roughly proportional to the chip area Switching activity (avg. number of transitions/cycle) ⌧Very data dependent ⌧A big portion due to glitches (real-delay) Clock frequency (f) ⌧Lowering only f decreases average power, but total energy is the same and throughput is worse 1.00 1 ...

  Consumption

MOSFET transistor I-V characteristics

course.ece.cmu.edu

Depletion Mode NMOSFET • Depletion mode FETs have a channel implanted such that there is conduction with V GS=0 • The operation is the same as the enhancement mode FET, but the threshold voltage is shifted •Vt is negative for depletion NMOS, and positive for depletion PMOS VGS n+ n+ VS VDS n+ p

  Dome, Transistor, Characteristics, Enhancement, Channel, Mosfets, Enhancement mode, Mosfet transistor i v characteristics

HDL Compiler for Verilog Reference Manual

course.ece.cmu.edu

Comments? E-mail your comments about Synopsys documentation to doc@synopsys.com HDL Compiler for Verilog Reference Manual Version 2000.05, May 2000

  Manual, Reference, Compiler, Verilog, Hdl compiler for verilog reference manual

A Primer on Memory Consistency and Cache Coherence

course.ece.cmu.edu

Daniel J. Sorin, Duke University Mark D. Hill and David A. Wood, University of Wisconsin, Madison ... We thank Blake Hechtman for implementing and testing (and debugging!) all of the coherence protocols in this primer. As the reader will soon …

  Daniel, Blake

Related documents

Computer Organization and Architecture Micro-Operations

aturing.umcs.maine.edu

cycle) has a number of smaller units —Fetch, indirect, execute, interrupt, etc • Each part of the cycle has a number of smaller steps called micro-operations —Discussed extensive in pipelining • Micro-ops are the fundamental or atomic operations of the processor Constituents of Program Execution The Fetch Cycle: 4 Registers

  Architecture, Cycle, Execute, Fetch, Fetch cycle

The RISC-V Processor

www.cs.cornell.edu

ARISC-V CPU with a (modified) Harvard architecture ... Fetch Decode Execute Memory WB A single cycle processor –this diagram is not 100% spatial. Basic CPU execution loop 1. Instruction Fetch 2. Instruction Decode 3. Execution (ALU) 4. Memory Access 5. Register Writeback

  Architecture, Cycle, Execute, Fetch, Fetch 2

Introduction to MARIE, A Basic CPU Simulator

marie.js.org

we don't need to increment the PC register here as it is already taken care of in the fetch part of the fetch-decode-execute cycle before it entered the subroutine. Program execution is resumed from where it was, and the program halts as the Halt instruction is executed. The major part of subroutines is that it can be reused.

  Cycle, Execute, Mirae, Fetch, Execute cycle

Computer Fundamentals - University of Cambridge

www.cl.cam.ac.uk

2 Aims & Objectives •This course aims to: –give you a general understanding of how a computer works –introduce you to assembly-level programming –prepare you for future courses. . . •At the end of the course youll be able to: –describe the fetch-execute cycle of a computer –understand the different types of information

  Cycle, Execute, Fetch, Execute cycle

Microprocessors - Tutorialspoint

www.tutorialspoint.com

The microprocessor follows a sequence: Fetch, Decode, and then Execute. Initially, the instructions are stored in the memory in a sequential order. The microprocessor fetches those instructions from the memory, then decodes it and executes those instructions till STOP instruction is reached. Later, it sends the result in binary to the output port.

  Tutorialspoint, Execute, Fetch

Related search queries

Architecture, Cycle, Fetch, Execute, Fetch Cycle, Fetch 2, MARIE, Execute cycle, Tutorialspoint