Transcription of VHDL Reference Manual
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VHDL Reference Manual
VHDL ReferenceManual096-0400-003 March 1997 Synario Design Automation, a division of Data I/O, has made every attempt toensure that the information in this document is accurate and complete. SynarioDesign Automation assumes no liability for errors, or for any incidental,consequential, indirect or special damages, including, without limitation, loss of use,loss or alteration of data, delays, or lost profits or savings, arising from the use ofthis document or the product which it part of this document may be reproduced or transmitted in any form or by anymeans, electronic or mechanical, for any purpose without written permission fromData Design Automation10525 Willows Road , Box 97046 Redmond, Washington 98073-9746 USAC orporate Switchboard.
VHDL Reference Manual 2-1 2. Language Structure VHDL is a hardware description language (HDL) that contains the features of conventional programming languages such as Pascal or C, logic description languages such as ABEL-HDL, and netlist languages such as EDIF. VHDL also includes design management features, and
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