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Zynq UltraScale+ RFSoC RF Data Converter v2.4 Gen 1/2/3 ...

Zynq UltraScale+ RFSoC RFData Converter Gen1/2/3 LogiCORE IP Product GuideVivado Design SuitePG269 ( ) November 30, 2020 Table of ContentsChapter 1: IP 2: Content by Design and 3: Product 4: Designing with the Core Configuration in the Vivado Design Modulator Correction ..139 Coarse Update Mode (Gen 3)..165PG269 ( ) November 30, 2020 UltraScale+ RFSoC RF Data Converter Gen 1/2/3 2 Send FeedbackBitstream to the AXI4-Stream 5: Design Flow and Generating the and 212 Chapter 6: Example 213RF-ADC Data Capture 214RF-DAC Data Stimulus Data 7: Test 222 Appendix A: 225 Changes from to from to from to from to from to from to B: Help on 230 Debug 232 Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux API ( ) November 30, 2020 UltraScale+ RFSoC RF Data Converter Gen 1/2/3 3 Send FeedbackAppendix D: RF E: Additional Resources and Legal Navigator and Design Read.

Characteristics (DS926). Note that Dual and Quad refers to the tile configuration and not the number of converters. F e a t u r e s • Up to 16 14-bit RF-DACs • Gen 1/Gen 2: Four 12-bit Dual RF-ADC tiles, or four 12-bit Quad RF-ADC tiles • Gen 3: Two or four 14-bit Dual RF-ADC tiles, and/or two or four 14-bit Quad RF-ADC tiles

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