The i2c bus
Found 7 free book(s)
Understanding the I2C Bus - TI.com
www.ti.comLogic Slave or Master R PU V Time V BUS V BUS SDA/SCL Logic Slave or Master R PU Electrical Characteristics www.ti.com 1 Electrical Characteristics I2C uses an open-drain/open-collector with an input buffer on the same line, which allows a single data line to be used for bidirectional data flow.
24AA128/24LC128/24FC128 Data Sheet - Microchip …
ww1.microchip.com24AA128/24LC128/24FC128 DS21191S-page 4 2010 Microchip Technology Inc. FIGURE 1-1: BUS TIMING DATA 13 TAA Output valid from clock (Note 2) — — — — 3500 900 900 400 ns 1.7V VCC 2.5V 2.5V VCC 5.5V 1.7V VCC 2.5V 24FC128 2.5V VCC 5.5V 24FC128 14 TBUF Bus free time: Time the bus must be free before a new
24AA02/24LC02B 2K I2C Serial EEPROM Data Sheet
ww1.microchip.com24AA02/24LC02B 1 Operation 1
Digole Serial:UART/I2C/SPI Character/Graphic …
www.digole.comDigital Solutions Serial Character/Graphic LCD/OLED User Manual Digole Serial:UART/I2C/SPI Character/Graphic LCD/OLED Display Module Programmer Manual (last updated: April 25, 2017) This manual may be modified without notice
5 Faults and Alarms - Simotech
www.simotech.co.zaIssue 03/05 Faults and Alarms MICROMASTER 440 Parameter List 6SE6400-5BB00-0BP0 303 5 Faults and Alarms 5.1 Fault messages In the event of a failure, the inverter switches off and a fault code appears on the
I2C Bus Pull-Up Resistor Calculation - TI.com
www.ti.comTitle: I2C Bus Pull-Up Resistor Calculation Author: Texas Instruments, Incorporated [SLVA689,*] Subject: Application Reports Keywords: SLVA689,SLVA689
AN10441 Level shifting techniques in I2C-bus design
www.nxp.comDocument information AN10441 Level shifting techniques in I2C-bus design Rev. 01 — 18 June 2007 Application note Info Content Keywords I2C-bus, level shifting Abstract Logic level shifting may be required when interfacing legacy devices with newer devices that use a smaller geometry process.