24AA02/24LC02B 2K I2C Serial EEPROM Data Sheet

1 2009 Microchip Technology 124AA02/24LC02 BDevice Selection TableFeatures: Single Supply with Operation down to for 24aa02 Devices, for 24lc02b Devices Low-Power CMOS Technology:- Read current 1 mA, Standby current 1 A, max. (I-temp) 2-Wire Serial Interface, I2C Compatible Schmitt Trigger inputs for Noise Suppression Output Slope Control to eliminate Ground Bounce 100 kHz and 400 kHz Clock Compatibility Page Write Time 3 ms, typical Self-Timed Erase/Write Cycle 8-Byte Page Write Buffer Hardware Write-Protect ESD Protection >4,000V More than 1 Million Erase/Write Cycles Data Retention >200 Years Factory Programming Available Packages include 8-lead PDIP, SOIC, TSSOP, DFN, TDFN, MSOP.

2 5-lead SOT-23 and SC-70 Pb-free and RoHS Compliant Temperature Ranges:- Industrial (I): -40 C to +85 C- Automotive (E): -40 C to +125 CDescription:The Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM. Thedevice is organized as one block of 256 x 8-bit memorywith a 2-wire Serial interface. Low-voltage designpermits operation down to , with standby andactive currents of only 1 A and 1 mA, 24XX02 also has a page write capability for up to8 bytes of data. The 24XX02 is available in thestandard 8-pin PDIP, surface mount SOIC, TSSOP, 2x3 DFN, 2x3 TDFN and MSOP packages and is also avail-able in the 5-lead SOT-23 and SC-70 TypesBlock DiagramPart NumberVCC RangeMax.

3 Clock FrequencyTemp. kHz(1) kHzI, ENote 1:100 kHz for VCC < , MSOPSOIC, TSSOPA0A1A2 VSS12348765 VCCWPSCLSDADFN/TDFNA0A1A2 VSSWPSCLSDAVCCSOT-23/SC-701543 SCLVssSDAWPVcc2 Note:Pins A0, A1 and A2 are not used by the 24XX02. (Nointernal connections).87651234HV EEPROM ArrayPage YDECXDECS ense ControlLatchesGenerator2K I2C Serial EEPROM24AA02/24LC02 BDS21709J-page 2 2009 Microchip Technology CHARACTERISTICSA bsolute Maximum Ratings ( ) inputs and outputs to VCC + temperature ..-65 C to +150 CAmbient temperature with power applied.

4 -40 C to +125 CESD protection on all 4kVTABLE 1-1:DC CHARACTERISTICS NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage tothe device. This is a stress rating only and functional operation of the device at those or any other conditionsabove those indicated in the operational listings of this specification is not implied. Exposure to maximum ratingconditions for extended periods may affect device CHARACTERISTICSI ndustrial (I): TA = -40 C to +85 C, VCC = + to + (E): TA = -40 C to +125 C, VCC = + to + , SCL and SDA pins D2 High-level input VCC V D3 VILLow-level input voltage VCCV D4 VHYSH ysteresis of SchmittTrigger VCC V(Note)D5 VOLLow-level output voltage = mA, VCC = leakage current 1 AVIN = VSS or VCCD7 ILOO utput leakage current 1 AVOUT = VSS or VCCD8 CIN, COUTPin capacitance(all inputs/outputs) 10pFVCC = (Note)

5 TA = 25 C, FCLK = 1 MHzD9 ICC writeOperating current 3mAVCC = , SCL = 400 kHzD10 ICC read D11 ICCSS tandby current 15 IndustrialAutomotiveSDA = SCL = VCCWP = VSSNote:This parameter is periodically sampled and not 100% tested. 2009 Microchip Technology 324AA02/24LC02 BTABLE 1-2:AC CHARACTERISTICSAC CHARACTERISTICSI ndustrial (I): TA = -40 C to +85 C, VCC = + to + (E): TA = -40 C to +125 C,VCC = + to + frequency VCC VCC < ( 24aa02 )2 THIGHC lock high time6004000 VCC VCC < ( 24aa02 )3 TLOWC lock low time13004700 VCC VCC < ( 24aa02 )4 TRSDA and SCL rise time (Note 1) VCC (Note 1) VCC < ( 24aa02 ) (Note 1)5 TFSDA and SCL fall time 300ns(Note 1)6 THD.

6 STAS tart condition hold time6004000 VCC VCC < ( 24aa02 )7 TSU:STAS tart condition setup time6004700 VCC VCC < ( 24aa02 )8 THD:DATData input hold time0 ns(Note 2)9 TSU:DATData input setup time100250 VCC VCC < ( 24aa02 )10 TSU:STOStop condition setup time6004000 VCC VCC < ( 24aa02 )11 TAAO utput valid from clock (Note 2) VCC VCC < ( 24aa02 )12 TBUFBus free time: Time the bus must be free before a new transmission can start13004700 VCC VCC < ( 24aa02 )13 TOFO utput fall time from VIH minimum to VIL maximum20+ VCC VCC < ( 24aa02 )14 TSPI nput filter spike suppression(SDA and SCL pins) 50ns(Notes 1 and 3)15 TWCW rite cycle time (byte or page) 5ms 16 Endurance1M cycles 25 C, (Note 4)Note 1:Not 100% tested.

7 CB = total capacitance of one bus line in :As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop :The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard :This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained from Microchip s web site at 4 2009 Microchip Technology 1-1:BUS TIMING DATAFIGURE 1-2:BUS TIMING START/STOP752489101211146 SCLSDAINSDAOUT376D410 StartStopSCLSDA 2009 Microchip Technology 524AA02 DESCRIPTIONSThe descriptions of the pins are listed in Table 2-1:PIN FUNCTION Address/Data Input/Output (SDA)SDA is a bidirectional pin used to transfer addressesand data into and out of the device.

8 Since it is an open-drain terminal, the SDA bus requires a pull-up resistorto VCC (typical 10 k for 100 kHz, 2 k for 400 kHz).For normal data transfer, SDA is allowed to changeonly during SCL low. Changes during SCL high arereserved for indicating Start and Stop Clock (SCL)The SCL input is used to synchronize the data transferto and from the (WP)The WP pin must be connected to either VSS or tied to VSS, normal memory operation is enabled(read/write the entire memory 00-FF).If tied to VCC, write operations are inhibited.

9 The entirememory will be write-protected. Read operations arenot , A1, A2 These A0, A1 and A2 pins are not used by the may be left floating or tied to either VSS or Not ConnectedA1222222 Not ConnectedA2333333 Not ConnectedVSS44444422 GroundSDA55555533 Serial Address/Data I/OSCL66666611 Serial ClockWP77777755 Write-Protect InputVCC88888844+ to Power Supply24AA02/24LC02 BDS21709J-page 6 2009 Microchip Technology DESCRIPTIONThe 24XX02 supports a bidirectional, 2-wire bus anddata transmission protocol. A device that sends dataonto the bus is defined as transmitter, while a devicereceiving data is defined as a receiver.

10 The bus has tobe controlled by a master device which generates theSerial Clock (SCL), controls the bus access and gener-ates the Start and Stop conditions, while the 24XX02works as slave. Both master and slave can operate astransmitter or receiver, but the master devicedetermines which mode is CHARACTERISTICSThe following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop , the following bus conditions have beendefined (Figure 4-1).