AXI IIC Bus Interface v2 - Xilinx

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The AXI IIC Bus Interface module provides the transaction interface to the AXI4-Lite interface. This core does not provide explicit electrical connectivity to the IIC bus. The design is expected to include bidirectional I/O buffers that implement open collector drivers for the sda and scl signals. You must also provide external pull-up devices to

  Devices, Interface, Xilinx