7 シリーズ FPGA GTP トランシーバー ... - Xilinx

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4 All other trademarks are the property of their respective owners.. 7 FPGA GTP UG482 ( ) 2016 6 21 .. 2012 1 3 . 2012 2 21 2-10 2-1 2-7 N N1 N2 A-4 . A-6 B-1 D-1 D-2 . 2012 1 1 . 2012 9 6 1 2 3 4 2-9 PLL0_FBDIV/. PLL1_FBDIV PLL0_FBDIV_45/ PLL0_FBDIV_45 . 2 3-2 3-5. 1 3-9 TXSTARTSEQ GEARBOX_MODE. 3-26 . 3-27 TXPI_SYNFREQ_PPM[2:0] TXPI_GREY_. SEL 3 TX 1 . 3 . 4-20 USE_PCS_CLK_PHASE_SEL ES_CLK_. PHASE_SE 4 2 3 . 4-25 RXBYTEISALIGNED 1 4-26. COMMA_ALIGN_LATENCY 4-42 GEARBOX_MODE . 5 A . B-1 . 2012 10 23 24 32 1 . 33 Artix-7 . 3-4 3-5 XC7A350T 4-3 PCIe . 5-2 5-3 XC7A350T 5-14 MGTAVCC_G[N] . MGTAVTT_G[N] A-9 A-10 . A-11 A-12 A-13 A-14 XC7A350T B-1 XC7A350T.. 2013 2 21 GTX GTP .. 2 : 2-2 2-12 2-13 2-14 2-15 2-16 2-17 . 2-6 1 2 2-8 1 4 . 39 2-14 5 . 6 2-17 47.

5 47 TX . 2-18 2 3 4 7 12 13 15 17 . 2-19 2-20 . 2-21 57 . GTP RX PMA 2-22 57 . GTP RX 47 . 62 . 66 2-28 2 . 2-29 3 7 2-30 3 7 . 71 74 . UG482 ( ) 2016 6 21 7 FPGA GTP .. 2013 2 21 3 : 97 TX 104 . ( ) 3-20 3-24 3 5 3-24 3 .. 4 : 4-3 4-4 4-5 4-6 5 6 4-7 12 . 135 142 4-14 147 . 4-15 4-18 4-17 3 . 5 153 RXRATE 154 . 180 RX 194 . 4-33 4-33 5 10 . 5 : 5-2 1 2 5-11 3 4 . A : A-4 A-14 . B : B-1 . 2013 4 15 2-22 2 24 3 . 2-29 2-30 DEN DRPEN 2-23 2-24 . 94 TX 3-15 . 100 TX 3-12 TX . 3-12 . 102 TX . ( ) . TX 4-2. 2 4-3 4-4 4-5 INCP IPCM 4-12. RXCDR_CFG 72 16 83 16 . 2013 8 28 XC7A35T-CSG325 (Preliminary) XC7A35T-FGG484 (Preliminary) . XC7A50T-CSG325 (Preliminary) XC7A50T-FGG484 (Preliminary) . XC7A75T-FGG484 XC7A75T-FGG676 . 2014 4 3 XC7A35T-CPG236 XC7A50T-CPG236 XC7Z015-CLG485.

6 1-3 SIM_VERSION 2-22 RX . RX PCS RX 61 RX . 2-29 2-30 DRPEN 4-11 RXOSCALRESET. RXOSINTDONE 4-27 RXCHARISK[3:0] . 5-2 5-3 / 5-3 . 5-8 5-9 5-10 / 247 SelectIO. CPG236 CSG325 CLG485 . ( A-1 A-2 A-3) A-4 B-1 . B-2 . 2014 11 19 XC7A15T (-PG236 -CPG236 -CLG485 ) 2-1 . O ODIV2 2-8 BGBYPASSB BGMONITORENB . BGPDB BGRCALOVRD RCALENB 2-17 2 . 65 PLL 2 71 . 2-31 DMONITORCLK . DMONFIFORESET . 2016 6 21 5-1 RXP RXN GTP . RXP RXN GTP .. 7 FPGA GTP UG482 ( ) 2016 6 21 .. 3.. 7.. 8.. 8. 1 : .. 9. 7 FPGA Transceivers Wizard .. 14.. 14.. 18. 2 : .. 21.. 24. PLL .. 34.. 37.. 62.. 66.. 68.. 71. 3 : . (TX) .. 75. FPGA TX .. 76. TX 8B/10B .. 83. TX .. 86. TX .. 94. TX .. 97. TX .. 104. TX .. 108. TX .. 108. TX PPM .. 112. TX .. 115. PCI Express TX .. 122. TX OOB.

7 124. 4 : . (RX) .. 127. RX .. 128. RX OOB .. 133. RX .. 142. RX CDR .. 144. RX .. 150. RX .. 154. 7 FPGA GTP 5. UG482 ( ) 2016 6 21 . RX .. 164. RX .. 164. RX .. 167. RX 8B/10B .. 176. RX .. 180. RX .. 194. RX .. 199. RX .. 208. RX .. 218. FPGA RX .. 226. 5 : .. 229.. 229.. 236.. 240. SelectIO .. 247. PCB .. 248. A : . CPG236 .. 252. CSG325 .. 253. CLG485 .. 254. FGG484 .. 255. FGG676 .. 256. FBG484 .. 258. SBG484 .. 259. FBG676 .. 260. FFG1156 .. 262. B : . C : 8B/10B . D : GTP DRP . 6 7 FPGA GTP . UG482 ( ) 2016 6 21 .. 7 FPGA 3 FPGA .. Artix -7 . Virtex -7 . Kintex -7 . FPGA 7 FPGA. GTP . 7 FPGA GTP 7 FPGA . ( ) .. 7 FPGA GTP GTP .. GTPE2_CHANNEL 1 GTP .. GTPE2_COMMON 2 PLL (PLL0 PLL1) .. (Q) 4 GTP 1 GTPE2_COMMON . 2 .. 1 . 2 . 3 . 4 . 5.

8 A . B . C 8B/10B . D GTP DRP . 7 FPGA GTP 7. UG482 ( ) 2016 6 21 .. IP .. 1. I/O . 8 7 FPGA GTP . UG482 ( ) 2016 6 21 . 1 .. 7 FPGA GTP 500Mb/s FPGA . 1-1 .. 1-1 : 7 FPGA . GTP GTX GTH. PCS 2 x x x 4 x x 8B/10B x x x 64B/66B 64B/67B x x x / x x x PRBS x x x / FIFO x x x FPGA x x x PMA 1 LC PLL x x 1 PLL x x 2 PLL x x x x (DFE) x x (LPM) . x x x . x x x PCI Express x x x SATA COM OOB x x x RX x x x 7 FPGA GTP 9. UG482 ( ) 2016 6 21 . 1 : . GTP .. PCI Express Interlaken 10Gb Attachment Unit Interface (XAUI) Reduced Pin eXtended Attachment Unit Interface (RXAUI). Common Packet Radio Interface (CPRI )/Open Base Station Architecture Initiative (OBSAI). OC-48. OTU-1. Serial RapidIO (SRIO). Serial Advanced Technology Attachment (SATA)/Serial Attached SCSI (SAS).

9 Serial Digital Interface (SDI). CORE Generator GTP .. LogiCORE IP 7 . FPGA (UG769) . Spartan -6 FPGA 7 FPGA GTP .. 2 . 2 PLL. CTLE ( ). RX 2D . I/O [ 1] .. 11 1-1 Artix -7 (XC7A100T) GTP . 8 GTP . 10 7 FPGA GTP . UG482 ( ) 2016 6 21 .. X-Ref Target - Figure 1-1. Artix-7 FPGA (XC7A100T). GTP Quad GTPE2_CHANNEL_X0Y7. GTPE2_ GTPE2_CHANNEL_X0Y6. Integrated COMMON_. Block for PCI X0Y1 GTPE2_CHANNEL_X0Y5. Express Operation GTPE2_CHANNEL_X0Y4. I/O CMT CMT I/O. Configuration Column Column Column Column GTP Quad GTPE2_CHANNEL_X0Y3. GTPE2_ GTPE2_CHANNEL_X0Y2. COMMON_. X0Y0 GTPE2_CHANNEL_X0Y1. GTPE2_CHANNEL_X0Y0. UG482_C1_01_110811. 1-1 : Artix-7 XC7A100T FPGA GTP . 7 FPGA .. 7 FPGA (UG470) .. 7 FPGA SelectIO (UG471) I/O .. 7 FPGA (UG472) MMCM ( . ) . 1-2 4 GTPE2_CHANNEL 1 GTPE2_COMMON.

10 7 FPGA GTP 11. UG482 ( ) 2016 6 21 . 1 : . X-Ref Target - Figure 1-2. GTPE2_CHANNEL GTPE2_CHANNEL GTPE2_CHANNEL GTPE2_CHANNEL. RX TX RX TX RX TX RX TX. PLL0 PLL1. GTPE2_COMMON. REFCLK Distribution IBUFDS_GTE2 IBUFDS_GTE2. UG482_c1_02_110811. 1-2 : GTP . 1 GTPE2_COMMON 4 GTPE2 . (Q) . GTPE2_COMMON 2 PLL (PLL0 PLL1) .. GTPE2_CHANNEL 1 .. 12 7 FPGA GTP . UG482 ( ) 2016 6 21 .. 1-3 GTPE2_CHANNEL . X-Ref Target - Figure 1-3. TX. TX TX PCIe Gearbox TX OOB Pre/ Beacon Driver and Post PCIe Emp SATA Pattern TX PIPE. OOB Generator Control FPGA. TX. Phase Interface TX Clock Adjust PISO Polarity Dividers FIFO 8B/10B. Encoder TX Phase TX Phase Interpolator Interpolator Controller TX-PMA TX-PCS. Clock From PLL0 or PLL1. To RX Parallel From RX Parallel Data From RX Parallel Data Data (Near-End (Far-End PMA Loopback) (Far-End PCS Loopback).)