Computer Architecture: Vector Processing: …
Example: 16 banks; can start one bank access per cycle Bank latency: 11 cycles Can sustain 16 parallel accesses if they go to different banks 16 Bank 0 Bank 1 MDR MAR Bank 2 Bank 15 MDR MAR MDR MAR MDR MAR Data bus Address bus CPU Slide credit: Derek Chiou
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Computer Architecture: Dataflow (Part I)
course.ece.cmu.eduComputer Architecture,” ACM Computing Surveys 1982. ! Veen, “Dataflow Machine Architecture,” ACM Computing Surveys 1986. ! Gurd et al., “The Manchester prototype dataflow computer,” CACM 1985. ! Arvind and Nikhil, “Executing a Program on the MIT Tagged-Token Dataflow Architecture,” IEEE TC 1990. !
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