Modelsim Simulation & Example VHDL Testbench
missing a VHDL generic “ram_block_type”. Quartus 10.1 has fixed this issue, so we will recompile the 10.1 altera_mf library, follow the same steps from slide 14 above, except point to the 10.1 directory structure Another way around these types of issues is to simply edit the VHDL.
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