Practical introduction to PCI Express with FPGAs
Xilinx Hard IP solution • User backend protocol same for all devices o Spartan – 6 o Virtex – 5 o Virtex – 6 o Virtex – 7 • Xilinx Local Link (LL) Protocol and ARM AXI • For new designs: use AXI • Most of the Xilinx PCIe app notes uses LL v 1.0
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