The Rocket Chip Generator
PC IF ID Int.EX EX MEM Commit WB FP.RF FP.EX1 FP.EX2 FP.EX3 To RoCC Accelerator DTLB Access D$ ITLB Access I$ Int.RF Decode Inst Figure 2: The Rocket core pipeline. Rocket is a 5-stage in-order scalar core generator that implements the RV32G and RV64G ISAs4. It has an MMU that supports page-based virtual memory, a non-blocking data cache, and
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