PCI Express Base Specification Revision 3 - akkit.org

1 PCI Express base Specification Revision November 10, 2010 2 Revision Revision History DATE Initial release. 07/22/2002 Incorporated Errata C1-C66 and 04/15/2003 Incorporated approved Errata and ECNs. 03/28/2005 Added GT/s data rate and incorporated approved Errata and ECNs. 12/20/2006 Incorporated Errata for the PCI Express base Specification , Rev. (February 27, 2009), and added the following ECNs: Internal Error Reporting ECN (April 24, 2008) Multicast ECN (December 14, 2007, approved by PWG May 8, 2008) Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008) Resizable BAR Capability ECN (January 22, 2008, updated and approved by PWG April 24, 2008) Dynamic Power Allocation ECN (May 24, 2008) ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008) Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008) Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated June 4, 2007) Extended Tag Enable Default ECN (September 5, 2008) TLP Processing Hints ECN (September 11, 2008)

2 TLP Prefix ECN (December 15, 2008) 03/04/2009 Added GT/s data rate, latest approved Errata, and the following ECNs: Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009) ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009) Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol Multiplexing ECN (17 June 2010) 11/10/2010 PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest Revision of this Specification .

3 Questions regarding the PCI Express base Specification or membership in PCI-SIG may be forwarded to: Membership Services E-mail: Phone: 503-619-0569 Fax: 503-644-6708 Technical Support DISCLAIMER This PCI Express base Specification is provided as is with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, Specification , or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this Specification . No license, Express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.

4 PCI, PCI Express , PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright 2002-2010 PCI-SIG PCI Express base Specification , REV. 3 Contents OBJECTIVE OF THE 27 DOCUMENT ORGANIZATION .. 27 DOCUMENTATION CONVENTIONS .. 28 TERMS AND ACRONYMS .. 29 REFERENCE 36 1. INTRODUCTION ..37 A THIRD GENERATION I/O 37 PCI Express 39 PCI Express FABRIC 41 Root 41 Endpoints .. 42 Switch .. 45 Root Complex Event 46 PCI Express to PCI/PCI-X 46 PCI Express FABRIC TOPOLOGY 46 PCI Express LAYERING 47 Transaction Layer.

5 48 Data Link Layer .. 48 Physical Layer .. 49 Layer Functions and Services .. 49 2. TRANSACTION LAYER Specification .. 53 TRANSACTION LAYER 53 Address Spaces, Transaction Types, and 54 Packet Format Overview .. 56 TRANSACTION LAYER PROTOCOL - PACKET 58 Common Packet Header Fields .. 58 TLPs with Data Payloads - Rules .. 61 TLP Digest Rules .. 65 Routing and Addressing Rules .. 65 First/Last DW Byte Enables 69 Transaction Descriptor .. 71 Memory, I/O, and Configuration Request 77 Message Request Rules .. 83 Completion Rules .. 97 TLP Prefix Rules .. 100 HANDLING OF RECEIVED 104 PCI Express base Specification , REV. 4 Request Handling Rules.

6 107 Completion Handling Rules .. 120 TRANSACTION 122 Transaction Ordering Rules .. 122 Update Ordering and Granularity Observed by a Read Transaction .. 126 Update Ordering and Granularity Provided by a Write Transaction .. 127 VIRTUAL CHANNEL (VC) 128 Virtual Channel Identification (VC ID) .. 130 TC to VC Mapping .. 131 VC and TC 132 ORDERING AND RECEIVE BUFFER FLOW 133 Flow Control Rules .. 134 DATA 145 ECRC Rules .. 145 Error Forwarding .. 149 COMPLETION TIMEOUT 151 LINK STATUS 151 Transaction Layer Behavior in DL_Down 151 Transaction Layer Behavior in DL_Up Status .. 153 3. DATA LINK LAYER Specification .. 155 DATA LINK LAYER 155 DATA LINK CONTROL AND MANAGEMENT STATE 157 Data Link Control and Management State Machine Rules.

7 158 FLOW CONTROL INITIALIZATION 160 Flow Control Initialization State Machine Rules .. 160 DATA LINK LAYER PACKETS (DLLPS) .. 164 Data Link Layer Packet Rules .. 164 DATA 169 169 LCRC, Sequence Number, and Retry Management (TLP Transmitter).. 169 LCRC and Sequence Number (TLP Receiver) .. 182 4. PHYSICAL LAYER Specification .. 191 191 LOGICAL 191 Encoding for GT/s and GT/s Data Rates .. 192 Encoding for GT/s and Higher Data 200 Link Equalization Procedure for GT/s Data Rate .. 218 Link Initialization and 226 Link Training and Status State Machine (LTSSM) 244 Link Training and Status State 247 Clock Tolerance Compensation.

8 314 Compliance Pattern in 8b/10b 317 Modified Compliance Pattern in 8b/10b Encoding .. 318 Compliance Pattern in 128b/130b 320 Modified Compliance Pattern in 128b/130b Encoding .. 322 PCI Express base Specification , REV. 5 ELECTRICAL 323 Electrical Specification 323 Interoperability Criteria for , , and GT/s Devices .. 323 Transmitter 325 Receiver Specifications .. 359 Low Frequency and Miscellaneous Signaling Requirements .. 382 Channel Specification .. 387 Refclk Specifications .. 400 Refclk Specifications for 408 5. POWER 413 413 Statement of 414 LINK STATE POWER 414 PCI-PM SOFTWARE COMPATIBLE 419 Device Power Management States (D-States) of a 419 PM Software Control of the Link Power Management 424 Power Management Event Mechanisms.

9 429 NATIVE PCI Express POWER MANAGEMENT 436 Active State Power Management (ASPM) .. 436 AUXILIARY POWER 455 Auxiliary Power 455 POWER MANAGEMENT SYSTEM MESSAGES AND 456 6. SYSTEM ARCHITECTURE .. 459 INTERRUPT AND PME 459 Rationale for PCI Express Interrupt 459 PCI Compatible INTx 460 INTx Emulation Software Model .. 460 Message Signaled Interrupt (MSI/MSI-X) 460 PME 462 Native PME Software Model .. 462 Legacy PME Software Model .. 463 Operating System Power Management 463 PME Routing Between PCI Express and PCI Hierarchies .. 463 ERROR SIGNALING AND 464 Scope .. 464 Error Classification .. 464 Error Signaling.

10 466 Error Logging .. 474 Sequence of Device Error Signaling and Logging Operations .. 478 Error Message Controls .. 480 Error Listing and Rules .. 481 Virtual PCI Bridge Error 486 Internal Errors .. 488 VIRTUAL CHANNEL 489 Introduction and Scope .. 489 PCI Express base Specification , REV. 6 TC/VC Mapping and Example 489 VC Arbitration .. 491 Isochronous Support .. 500 DEVICE 502 LOCKED 503 503 Initiation and Propagation of Locked Transactions - 504 Switches and Lock - 505 PCI Express /PCI Bridges and Lock - Rules .. 506 Root Complex and Lock - 506 Legacy 506 PCI Express Endpoints .. 506 PCI Express RESET - 506 Conventional Reset.