N-Channel 30-V (D-S) Fast Switching MOSFET - Vishay

1 Vishay SiliconixSi7114 DNDocument Number: 73039S-80581-Rev. E, 30-V (D-S) fast Switching MOSFETFEATURES Halogen-free Option Available TrenchFET Gen II Power MOSFET New Low Thermal Resistance PowerPAK Package with Low mm Profile 100 % Rg TestedAPPLICATIONS Synchronous RectificationPRODUCT SUMMARY VDS (V)RDS(on) ( )ID (A)Qg (Typ.) at VGS = 10 V at VGS = V mmPowerPAK 1212-8 Bottom ViewOrdering Information:Si7114DN-T1-E3 (Lead (Pb)-free)Si7114DN-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFETGDSN otes:a. Surface Mounted on 1" x 1" FR4 See Solder Profile ( ). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposedcopper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed andis not required to ensure adequate bottom side solder Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.

2 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise notedParameter Symbol 10 sSteady State Unit Drain-Source Voltage VDS30 VGate-Source Voltage VGS 20 Continuous Drain Current (TJ = 150 C)aTA = 25 = 70 Drain CurrentIDM60 Continuous Source Current (Diode Conduction) Avalanche CurrentL = 0 1 mHIAS29 Single Avalanche EnergyEAS42mJMaximum Power DissipationaTA = 25 = 70 Junction and Storage Temperature Range TJ, Tstg- 55 to 150 CSoldering Recommendations (Peak Temperature)b, c260 THERMAL RESISTANCE RATINGSP arameter Symbol TypicalMaximumUnit Maximum Junction-to-Ambientat 10 sRthJA2433 C/WSteady State6581 Maximum Junction-to-Case (Drain)Steady COMPLIANT Number: 73039S-80581-Rev.

3 E, 17-Mar-08 Vishay SiliconixSi7114 DNNotes:a. Pulse test; pulse width 300 s, duty cycle 2 %.b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device CHARACTERISTICS 25 C, unless otherwise notedMOSFET SPECIFICATIONS TJ = 25 C, unless otherwise notedParameter Symbol Test Conditions StaticGate Threshold VoltageVGS(th) VDS = VGS, ID = 250 A 13 VGate-Body LeakageIGSSVDS = 0 V, VGS = 20 V 100 nAZero Gate Voltage Drain CurrentIDSSVDS = 30 V, VGS = 0 V 1 AVDS = 30 V, VGS = 0 V, TJ = 55 C 5On-State Drain CurrentaID(on) VDS 5 V, VGS = 10 V 40 ADrain-Source On-State ResistanceaRDS(on)

4 VGS = 10 V, ID = A VGS = V, ID = A Transconductanceagfs VDS = 15 V, ID = A 77 SDiode Forward VoltageaVSDIS = A, VGS = 0 V Gate ChargeQg VDS = 15 V, VGS = V, ID = A ChargeQgs ChargeQgd ResistanceRgf = 1 Tu r n - O n D e l a y T i m etd(on) VDD = 15 V, RL = 15 ID 1 A, VGEN = 10 V, Rg = 6 1015nsRise Timetr1015 Turn-Off Delay Timetd(off) 4570 Fall Timetf1015 Source-Drain Reverse Recovery TimetrrIF = A, di/dt = 100 A/ s3060 Body Diode Reverse Recovery ChargeQrrIF = A, di/dt = 100 A/ s1938nCOutput = 10 thru 4 V3 VVDS - Drain-to-Source Voltage (V)- Drain Current (A)IDTransfer = 125 C- 55 CVGS - Gate-to-Source Voltage (V)- Drain Current (A)ID25 CDocument Number: 73039S-80581-Rev. E, SiliconixSi7114 DNTYPICAL CHARACTERISTICS 25 C, unless otherwise notedOn-Resistance vs. Drain CurrentGate ChargeSource-Drain Diode Forward 1224364860- On-Resistance ( )RDS(on)ID - Drain Current (A)VGS = VVGS = 10 V0246810051015202530 VDS = 15 VID = A- Gate-to-Source Voltage (V)Qg - Total Gate Charge (nC)VGSVSD - Source-to-Drain Voltage (V) = 25 C60101- Source Current (A)ISTJ = 150 CCapacitanceOn-Resistance vs.

5 Junction TemperatureOn-Resistance vs. Gate-to-Source Voltage05001000150020002500051015202530 CossCissVDS - Drain-to-Source Voltage (V)C - Capacitance (pF) 50- 250255075100125150 VGS = 10 VID = ATJ - Junction Temperature ( C)RDS(on) - On-Resistance(Normalized) On-Resistance ( )RDS(on)VGS - Gate-to-Source Voltage (V)ID = AID = 5 Number: 73039S-80581-Rev. E, 17-Mar-08 Vishay SiliconixSi7114 DNTYPICAL CHARACTERISTICS 25 C, unless otherwise notedThreshold Voltage- 50- 250255075100125150ID = 250 AVariance (V)VGS(th)TJ - Temperature ( C)Single Pulse Power, (s)3020 Power (W) Operating = 25 CSingle Pulse- Drain Current (A) LimitedID(on)LimitedLimited byRDS(on)* BVDSS LimitedP(t) = 10 DCP(t) = 1P(t) = (t) = (t) = (t) = - Drain-to-Source Voltage (V)* VGS > minimum VGS at which RDS(on) is specifiedNormalized Thermal Transient Impedance, PulseDuty Cycle = Wave Pulse Duration (s)Normalized Effective TransientThermal Impedance1.

6 Duty Cycle, D =2. Per Unit Base = RthJA = 65 C/W3. TJM - TA = PDMZthJA(t)t1t2t1t2 Notes:4. Surface MountedPDMD ocument Number: 73039S-80581-Rev. E, SiliconixSi7114 DNTYPICAL CHARACTERISTICS 25 C, unless otherwise notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see Thermal Transient Impedance, PulseDuty Cycle = Wave Pulse Duration (s)Normalized Effective TransientThermal ImpedancePackage Siliconix Revison: 09-Jan-171 Document Number: 71656 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT 1212-8, (Single / Dual) 0 -12 0 -12 : S16-2667-Rev.

7 M, 09-Jan-17 DWG: 5882 Notes1. Inch will govern2 Dimensions exclusive of mold gate burrs3. Dimensions exclusive of mold flash and cutting burrsBackside view of single padBackside view of dual padDetail ZD1D2D1E1cA5418D243H21 eb E2 LbD3(2x)4321A1 ZKK1 WMD4E3E4D5 KHE4E2LD2D4E3D5L122 DEH Vishay SiliconixAN822 Document Number 1212 Mounting and Thermal ConsiderationsJohnson ZhaoMOSFETs for Switching applications are now availablewith die on resistances around 1 m and with thecapability to handle 85 A. While these die capabilitiesrepresent a major advance over what was availablejust a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvi-ous that degradation of a high performance die by thepackage is undesirable. PowerPAK is a new packagetechnology that addresses these issues. The PowerPAK1212-8 provides ultra-low thermal impedance in asmall package that is ideal for space-constrainedapplications.

8 In this application note, the PowerPAK1212-8 s construction is described. Following this,mounting information is presented. Finally, thermaland electrical performance is PowerPAK PACKAGEThe PowerPAK 1212-8 package (Figure 1) is a deriva-tive of PowerPAK SO-8. It utilizes the same packagingtechnology, maximizing the die area. The bottom of thedie attach pad is exposed to provide a direct, low resis-tance thermal path to the substrate the device ismounted on. The PowerPAK 1212-8 thus translatesthe benefits of the PowerPAK SO-8 into a smallerpackage, with the same level of thermal performance.(Please refer to application note PowerPAK SO-8 Mounting and Thermal Considerations. )The PowerPAK 1212-8 has a footprint area compara-ble to TSOP-6. It is over 40 % smaller than standardTSSOP-8. Its die capacity is more than twice the sizeof the standard TSOP-6 s. It has thermal performancean order of magnitude better than the SO-8, and 20times better than TSSOP-8.

9 Its thermal performance isbetter than all current SMT packages in the market. Itwill take the advantage of any PC board heat sinkcapability. Bringing the junction temperature down alsoincreases the die efficiency by around 20 % comparedwith TSSOP-8. For applications where bigger pack-ages are typically required solely for thermal consider-ation, the PowerPAK 1212-8 is a good the single and dual PowerPAK 1212-8 utilize thesame pin-outs as the single and dual PowerPAK low mm PowerPAK height profile makes bothversions an excellent choice for applications withspace 1212 SINGLE MOUNTINGTo take the advantage of the single PowerPAK 1212-8 sthermal performance see Application Note 826,Recommended Minimum Pad Patterns With OutlineDrawing Access for Vishay Siliconix mosfets . Clickon the PowerPAK 1212-8 single in the index of thisdocument. In this figure, the drain land pattern is given to make fullcontact to the drain pad on the PowerPAK land pattern can be extended to the left, right, andtop of the drawn pattern.

10 This extension will serve toincrease the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to thePC board and therefore to the ambient. Note thatincreasing the drain land area beyond a certain pointwill yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditionsof board configuration, copper weight, and layer stack,experiments have found that adding copper beyond anarea of about to in2 of will yield little improve-ment in thermal 1. PowerPAK 1212 Number 7168103-Mar-06 Vishay SiliconixAN822 PowerPAK 1212 DUALTo take the advantage of the dual PowerPAK 1212-8 sthermal performance, the minimum recommendedland pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With OutlineDrawing Access for Vishay Siliconix mosfets . Clickon the PowerPAK 1212-8 dual in the index of this gap between the two drain pads is 10 mils.