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Spartan-6 FPGA Clocking Resources - Xilinx

Spartan-6 FPGA Clocking Resources www.xilinx.com UG382 (v1.10) June 19, 2015 02/16/2011 1.5 Added BUFGMUX routing restrictions for DCM and PLL programming clock and BUFGMUX ASYNC usage to Clock Buffers and Multiplexers.

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