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Design and Layout Guidelines for the CDCVF2505 Clock ...
www.ti.comSCAA045 2 Design and Layout Guidelines for the CDCVF2505 Clock Driver 1 Introduction The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver (refer to [1] for details). It uses a PLL to phase- and frequency-align the input (CLKIN) and
CDCVF2505 3.3-V Clock Phase Lock-Loop Clock Driver ...
www.ti.comPACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2)