Search results with tag "Layout guidelines for the cdcvf2505 clock driver"

Design and Layout Guidelines for the CDCVF2505 Clock ...

SCAA045 2 Design and Layout Guidelines for the CDCVF2505 Clock Driver 1 Introduction The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver (refer to [1] for details). It uses a PLL to phase- and frequency-align the input (CLKIN) and

  Guidelines, Drivers, Clock, Layout, Layout guidelines for the cdcvf2505 clock, Cdcvf2505, Layout guidelines for the cdcvf2505 clock driver, Clock driver