SN54/74LS90 SN54/74LS92 DECADE COUNTER; …

1 SN54/74LS90 . SN54/74LS92 . DECADE counter ; SN54/74LS93. DIVIDE-BY-TWELVE counter ;. 4-BIT BINARY counter . DECADE counter ;. The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a di- DIVIDE-BY-TWELVE counter ;. vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or 4-BIT BINARY counter . divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi- LOW POWER SCHOTTKY. tion on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9). Low Power Consumption .. Typically 45 mW J SUFFIX. High Count Rates .. Typically 42 MHz CERAMIC. Choice of Counting Modes.

2 BCD, Bi-Quinary, Divide-by-Twelve, CASE 632-08. Binary 14. 1. Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES LOADING (Note a). HIGH LOW N SUFFIX. PLASTIC. CP0 Clock (Active LOW going edge) Input to CASE 646-06. 2 Section 14. CP1 Clock (Active LOW going edge) Input to 1. 5 Section (LS90), 6 Section (LS92). CP1 Clock (Active LOW going edge) Input to 8 Section (LS93) D SUFFIX. MR1, MR2 Master Reset (Clear) Inputs SOIC. 14. MS1, MS2 Master Set (Preset-9, LS90) Inputs CASE 751A-02. 1. Q0 Output from 2 Section (Notes b & c) 10 5 ( ) Q1, Q2, Q3 Outputs from 5 (LS90), 6 (LS92), 10 5 ( ) 8 (LS93) Sections (Note b). ORDERING INFORMATION. NOTES: a. 1 TTL Unit Load ( ) = 40 A mA LOW. SN54 LSXXJ Ceramic b. The Output LOW drive factor is for Military, (54) and 5 for commercial (74) SN74 LSXXN Plastic b. Temperature Ranges. SN74 LSXXD SOIC. c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.

3 D. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns. LOGIC SYMBOL. LS90 LS92 LS93. 6 7. 1 2. MS. 14 CP0 14 CP0 14 CP0. 1 CP1 1 CP1 1 CP1. MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3. 1 2 1 2 1 2. 2 3 12 9 8 11 6 7 12 11 9 8 2 3 12 9 8 11. VCC = PIN 5 VCC = PIN 5 VCC = PIN 5. GND = PIN 10 GND = PIN 10 GND = PIN 10. NC = PINS 4, 13 NC = PINS 2, 3, 4, 13 NC = PIN 4, 6, 7, 13. FAST AND LS TTL data . 5-1. SN54/74LS90 SN54/74LS92 SN54/74LS93. LOGIC DIAGRAM CONNECTION DIAGRAM. DIP (TOP VIEW). LS90. 6. MS1 CP1 1 14 CP0. MS2. 7. MR1 2 13 NC. S S S S. J DQ J DQ J DQ R DQ. 14 MR2 3 12 Q0. CP0 CP CP CP CP. NC 4 11 Q3. KC Q KC Q KC Q SC Q. D D D D. VCC 5 10 GND. 1. CP1 MS1 6 9 Q1. 2. MR1 MS2 7 8 Q2. 12 9 8 11. MR2. 3 Q0 Q1 Q2 Q3. NC = NO INTERNAL CONNECTION. = PIN NUMBERS NOTE: VCC = PIN 5 The Flatpak version has the same GND = PIN 10 pinouts (Connection Diagram) as the Dual In-Line Package.

4 LOGIC DIAGRAM CONNECTION DIAGRAM. DIP (TOP VIEW). LS92. CP1 1 14 CP0. NC 2 13 NC. J Q J Q J Q J Q. 14. CP0 NC 3 12 Q0. CP CP CP CP. KC Q KC Q KC Q KC Q NC 4 11 Q1. D D D D. VCC 5 10 GND. 1. CP1 MR1 6 9 Q2. 6. MR1 12 11 9 8 MR2 7 8 Q3. MR2. 7 Q0 Q1 Q2 Q3. NC = NO INTERNAL CONNECTION. = PIN NUMBERS NOTE: VCC = PIN 5 The Flatpak version has the same GND = PIN 10 pinouts (Connection Diagram) as the Dual In-Line Package. LOGIC DIAGRAM CONNECTION DIAGRAM. DIP (TOP VIEW). LS93. CP1 1 14 CP0. J Q J Q J Q J Q MR1 2 13 NC. 14. CP0 CP CP CP CP. MR2 3 12 Q0. KC Q KC Q KC Q KC Q. D D D D. NC 4 11 Q3. 1. CP1 VCC 5 10 GND. 2. MR1 NC 6 9 Q1. 12 9 8 11. MR2. 3 Q0 Q1 Q2 Q3 NC 7 8 Q2. = PIN NUMBERS NC = NO INTERNAL CONNECTION. VCC = PIN 5 NOTE: GND = PIN 10 The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. FAST AND LS TTL data . 5-2. SN54/74LS90 SN54/74LS92 SN54/74LS93.

5 FUNCTIONAL DESCRIPTION. The LS90, LS92, and LS93 are 4-bit ripple type DECADE , C. Divide-By-Two and Divide-By-Five counter No external Divide-By-Twelve, and Binary Counters respectively. Each interconnections are required. The first flip-flop is used as a device consists of four master/slave flip-flops which are binary element for the divide-by-two function (CP0 as the internally connected to provide a divide-by-two section and a input and Q0 as the output). The CP1 input is used to obtain divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight binary divide-by-five operation at the Q3 output. (LS93) section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW. LS92. clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, A. Modulo 12, Divide-By-Twelve counter The CP1 input decoded output signals are subject to decoding spikes and must be externally connected to the Q0 output.

6 The CP0 in- should not be used for clocks or strobes. The Q0 output of put receives the incoming count and Q3 produces a sym- each device is designed and specified to drive the rated metrical divide-by-twelve square wave output. fan-out plus the CP1 input of the device. B. Divide-By-Two and Divide-By-Six counter No external A gated AND asynchronous Master Reset (MR1 MR2) is interconnections are required. The first flip-flop is used as a provided on all counters which overrides and clocks and binary element for the divide-by-two function. The CP1 in- resets (clears) all the flip-flops. A gated AND asynchronous put is used to obtain divide-by-three operation at the Q1. Master Set (MS1 MS2) is provided on the LS90 which and Q2 outputs and divide-by-six operation at the Q3 out- overrides the clocks and the MR inputs and sets the outputs to put. nine (HLLH). Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices LS93.

7 May be operated in various counting modes. A. 4-Bit Ripple counter The output Q0 must be externally connected to input CP1. The input count pulses are applied LS90 to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are A. BCD DECADE (8421) counter The CP1 input must be ex- performed at the Q0, Q1, Q2, and Q3 outputs as shown in ternally connected to the Q0 output. The CP0 input receives the truth table. the incoming count and a BCD count sequence is pro- B. 3-Bit Ripple counter The input count pulses are applied duced. to input CP1. Simultaneous frequency divisions of 2, 4, and B. Symmetrical Bi-quinary Divide-By-Ten counter The Q3 8 are available at the Q1, Q2, and Q3 outputs. Independent output must be externally connected to the CP0 input. The use of the first flip-flop is available if the reset function coin- input count is then applied to the CP1 input and a divide-by- cides with reset of the 3-bit ripple-through counter .

8 Ten square wave is obtained at output Q0. FAST AND LS TTL data . 5-3. SN54/74LS90 SN54/74LS92 SN54/74LS93. LS90 LS92 AND LS93. MODE SELECTION MODE SELECTION. RESET / SET INPUTS OUTPUTS RESET. OUTPUTS. INPUTS. MR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3. MR1 MR2 Q0 Q1 Q2 Q3. H H L X L L L L. H H X L L L L L H H L L L L. X X H H H L L H L H Count L X L X Count H L Count X L X L Count L L Count L X X L Count H = HIGH Voltage Level X L L X Count L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level X = Don't Care LS90 LS92 LS93. BCD COUNT SEQUENCE TRUTH TABLE TRUTH TABLE. OUTPUT OUTPUT OUTPUT. COUNT COUNT COUNT. Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3. 0 L L L L 0 L L L L 0 L L L L. 1 H L L L 1 H L L L 1 H L L L. 2 L H L L 2 L H L L 2 L H L L. 3 H H L L 3 H H L L 3 H H L L. 4 L L H L 4 L L H L 4 L L H L. 5 H L H L 5 H L H L 5 H L H L. 6 L H H L 6 L L L H 6 L H H L.

9 7 H H H L 7 H L L H 7 H H H L. 8 L L L H 8 L H L H 8 L L L H. 9 H L L H 9 H H L H 9 H L L H. NOTE: Output Q0 is connected to Input 10 L L H H 10 L H L H. CP1 for BCD count. 11 H L H H 11 H H L H. NOTE: Output Q0 is connected to Input 12 L L H H. CP1. 13 H L H H. 14 L H H H. 15 H H H H. NOTE: Output Q0 is connected to Input CP1. FAST AND LS TTL data . 5-4. SN54/74LS90 SN54/74LS92 SN54/74LS93. GUARANTEED OPERATING RANGES. Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 V. 74 TA Operating Ambient Temperature Range 54 55 25 125 C. 74 0 25 70. IOH Output Current High 54, 74 mA. IOL Output Current Low 54 mA. 74 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified). Limits S b l Symbol P. Parameter Min Typ Max U i Unit T. Test C. Conditions di i Guaranteed Input HIGH Voltage for VIH Input HIGH Voltage V. All Inputs 54 Guaranteed Input p LOW Voltage g for VIL Input LOW Voltage V.

10 74 All Inputs VIK Input Clamp Diode Voltage V VCC = MIN, IIN = 18 mA. 54 V VCC = MIN,, IOH = MAX,, VIN = VIH. VOH Output HIGH Voltage 74 V or VIL per Truth Table 54, 74 V IOL = mA VCC = VCC MIN, VOL Output LOW Voltage VIN = VIL or VIH. 74 V IOL = mA per Truth Table 20 A VCC = MAX, VIN = V. IIH Input HIGH Current mA VCC = MAX, VIN = V. Input LOW Current MS, MR IIL CP0 mA VCC = MAX, VIN = V. CP1 (LS90, LS92) CP1 (LS93) IOS Short Circuit Current (Note 1) 20 100 mA VCC = MAX. ICC Power Supply Current 15 mA VCC = MAX. Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL data . 5-5. SN54/74LS90 SN54/74LS92 SN54/74LS93. AC CHARACTERISTICS (TA = 25 C, VCC = V, CL = 15 pF). Limits LS90 LS92 LS93. S b l Symbol P. Parameter Min Typ Max Min Typ Max Min Typ Max U i Unit fMAX CP0 Input Clock Frequency 32 32 32 MHz fMAX CP1 Input Clock Frequency 16 16 16 MHz tPLH Propagation Delay, 10 16 10 16 10 16.