100GE and 40GE PCS for EEE - IEEE 802

1 100GE and 40ge PCS OverviewIEEE November 2008 Dallas2 Agenda 40ge / 100GE Architecture PCS and MLD layer details Possible XL/CGMII Interface Alignment details Alignment performance metrics Clocking example Skew Summary340GE/ 100GE Generic ArchitectureMAC - Media Access ControlXL/CGMIIMDIPCS1 PMAPMDA pplicationPresentationSessionTransportNe tworkData LinkPhysicalReconciliationMAC Control (optional)LLC or Other MAC ClientMEDIUMn lanesm lanesHigher Layers1: Includes MLD functionalityFEC22: For 40ge Backplane4 Proposed 100GE / 40ge PCS 10 GBASE-R 64B/66B based PCS Run at 100 Gbps or 40 Gbps serial rateIncludes 66 bit block encoding and scrambling Multi-Lane DistributionData is distributed across n virtual lanes 66 bit blocks at a time Round robin distributionPeriodic alignment blocks are added to each virtual lane to allow deskew in the rx PCS PMA maps n lanes to m lanesPMA is simple bit level muxingDoes not know or care about PCS coding Alignment and static skew compensation is done in the Rx PCS only5 Striping Mechanism4TX

2 PCSXLGMIPCS Functions:64/66 bit encodingScramblingRound robin block distributionPeriodic alignment block addition32143218765 AAAAThis example is 40ge with 4 electrical and 4 optical lanesEach Block is a 66 bit Block6 Alignment Mechanism 40ge ExampleTX PCS43218765 AAAASkewSkewSkewSkewRX PCS4321765 AAAA11159 Alignment43218765RX PCS Functions:Re-Align 66 bit blocks Remove the Alignment blocksThen descramble and decode 7 Key Concept Virtual Lanes Virtual lanes may or may not correspond to physical lanes Virtual lanes are created by distributing PCS encoded data in a round robin fashion, on a 66 bit block basis The number of virtual lanes generated is scaled to the Least Common Multiple (LCM) of the n lane electrical interface and the m lane PMDThis allows all data (bits)

3 From one virtual lane to be transmitted over the same electrical and optical lane combinationThis ensures that the data from a virtual lane is always received with the correct bit order at the Rx MLD The alignment markers allow the Rx PCS to perform skew compensation, realign all the virtual lanes, and reassemble a single 100G or 40G aggregate stream (with all the 64B/66B blocks in the correct order) Virtual lanes support a very simple mapping (blind bit level interleaving/disinterleaving) to electrical and optical interface of different lane widths (and lane widths that evolve over time, get narrower)8 Bit Flow Through 100GE 4 lane PMD 20 VLs 10 Electrical lanes 4 Optical lanes With Skew, VLs move around RX MLD puts things back in order9 Virtual Lanes Generation.

4 Another viewWord #1 Word #2 Word #nWord #n+1 Word #n+2 Word #2n+1 Simple Word LevelRound Robin Virtual Lane 1#1#n+1#2n+1 Virtual Lane 2#2#n+2#2n+2 Virtual Lane n#n#2n#3nMM1M2 MnPeriodic 66-bit alignment words (used by Rx to identify and align virtual lanes) Aggregate Stream(of scrambled 64B/66B words)= 66-bit word MM1M2Mn10 Virtual Lanes Muxing .. Another view 100G Aggregate Stream(of scrambled 64B/66B words)12201 CAUI 1 CAUI 2 CAUI 10= 66-bit word = single bit VL 1VL 2VL 7VL 8VL 19VL 20VL 1VL 2VL 7VL 8VL 191 16 VL 1VL 2VL 3VL4VL5VL 16VL 17VL 18VL19VL202 3 4 5 17 18 19 20 PMDPMD VL 20 WordDistributor64/66B Encoder BitMuxBitMuxBitMux40G Aggregate Stream(of scrambled 64B/66B words)1241VL 1VL 2VL 3VL 4 PMPMPMPMXLAUI 1 XLAUI 2 XLAUI 3 XLAUI 4 WordDistributorMMMMMMMMMMMLD DistributionPMA 10:4 PMA 4:111 How Many Virtual Lanes are Needed?

5 4, 2, 1 Electrical Lane Widths44, 2, 1 Virtual Lanes NeededPMD Lane Widths 4 VLs For 40ge , this covers all of the possible combinations of lanes:10, 5, 4, 2, 1 Electrical Lane Widths2010, 5, 4, 2, 1 Virtual Lanes NeededPMD Lane Widths 20 VLs For 100GE , this covers all of the possible combinations of lanes:12 PCS Encoding Same 10 GBASE-R PCS (Clause 49) encodingNot used since we have 8B alignmentOnly block type used for ordered sets13 PCS Scrambling Identical 10 GBASE-R PCS (Clause 49) scramblerRuns at 40 Gbps or 100 Gbps now14 PCS Idle Deletion/Insertion rules Straight from (except for highlighted text).

6 Idle insertion or deletion occurs in groups of eightIdle charactersIdle characters are added following idle or ordered_setsIdle characters are not added while data is being receivedWhen deleting idles, the minimum IPG of one characteris maintainedSequence ordered_sets are deleted to adapt between clock ratesSequence ordered_set deletion occurs only when two consecutive sequence ordered_sets have been received and deletes only one of the twoOnly idles are inserted for clock compensation15 PCS Bit OrderD407D307D707D607D507D107D207D007 TXD<0>TXD<63>XL/CGMIIO utput of EncoderScramblerSync HeaderS407S307S707S607S507S107S207S007S4 07S307S707S607S507S107S207S007 Out to Virtual Lane DistributionOutput of Scrambler66b TransmitBlock16 Alignment Proposal

7 Send alignment on a fixed time basis Alignment word also identifies virtual lanes Sent every 16384 66bit blocks on each virtual lane at the same time~216usec for 20 VLs @ 100G~108usec for 4 VLs @ 40G It temporarily interrupts packets Takes only (60 PPM) of the Bandwidth Rate Adjust FIFO will delete enough IPG so that the MAC still runs at or with the interface running at Word ProposalRequirements: Significant transitions and DC balanced word is not scrambled Keep in 66 bit form, but no relation to 10 GBASE-R is needed But why not keep it close?

8 Because of the clock wander concerns Contains Virtual Lane Identifier10 Proposed Alignment Word This is DC balanced No relationship to the normal 10 GBASE-R blocks Added after and removed before 64/66 processing Alignment block is periodic, no Hamming distance concerns with 64/66 block typesVL~VL18 Alignment Word Proposal 100 GEThe encoding of the VL markers is as follows (based on x58+ x39+ 1 scrambler output):5F, 66, 2A, 6F18A0, 24, 76, DF8C0, F0, E5, E91968, C9, FB, 389AD, D6, B7, 35177B, 45, 66, FA7C4, 31, 4C, 30169A, 4A, 26, 15635, 36, CD, EB15DD, 14, C2, 50583, C7, CA, B514F5, 07, 09, 0B41A, F8, BD, AB134D, 95, 7B, 1035C, B9, B2, CD1259, 4B, E8, B02B9, 91, 55, B8119D, 71, 8E, 171FD, 6C, 99, DE10C1,68,21,F4032 Bit encodingVL Number32 Bit encodingVL NumberNote that data is played out in VL order, 0, 1, 2.

9 19, 0, Word Proposal 40 GEThe encoding of the VL markers is as follows (based on x58+ x39+ 1 scrambler output):4D, 95, 7B, 10359, 4B, E8, B029D, 71, 8E, 171C1,68,21,F4032 Bit encodingVL NumberNote that data is played out in VL order, 0, 1, 2, 3, Paths Through the LinkRx PCSTx PCS2:1023456810111213141516 187917191:22:12:12:12:12:12:12:12:12:11: 21:21:21:21:21:21:21:21:21 Skew on input electrical interface determines which optical lane VL 0 passes throughPMAPMDPMDPMASkew on optical interface and previous electrical interface determines which output electrical lane VL 0 passes throughVL 0 can appear on any of the red outputs depending on the skew of the electrical and optical interfacesNote: These possible paths are based on a 10:4 and 4:10 function based on round-robin distribution.

10 Other arrangements which give different paths are possible. 21 Virtual Lane Location on the Receive SideDue to how virtual lanes are multiplexed, and due to skew, and in order to be future proof:All receivers must support receiving a transmitted virtual lane on any received virtual laneThis is true for 100GE and 40GE22 Finding VL Alignment After reception in the rx MLD, you have x VLs, each skewed and transposed First you find 66bit alignment on each VLEach VL is a stream of 66 bit blocksSame mechanism as 10 GBASE-R (64 valid 2 bit frame codes in a row)