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1 JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD79 CMARCH 2003 JEDECSTANDARDD ouble Data Rate (DDR)SDRAM Specification(Revision of JESD79B) NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequently reviewed and approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, materials, or processes.

2 By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach toproduct specification and application, principally from the solid state device manufacturer the JEDEC organization there are procedures whereby a JEDEC standard or publication maybe further processed and ultimately become an EIA standard. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and sugg estions relative to the content of this JEDEC standard or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or Published by JEDEC Solid State Technology Association 2003 2500 Wilson Boulevard Arlington, VA 22201-3834 This documentmay be downloaded free of charge, however JEDEC retains the copyright on this material.

3 By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada (1-800-854-7179), International (303-397-7956) Printed in the All rights reserved PLEASE! DON T VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 79C -i- DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION (From JEDEC Board Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee on DRAM Parametrics.)

4 Standard No. 79 Revision Log. Release 1, June 2000 Release 2, May 2002 Release C, March 2003 Scope This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices. JEDEC Standard No. 79C -ii- JESD79 CPage 1 DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION16 M X4 (4 M X4 X4 banks), 8 M X8 (2 M X8 X4 banks), 4 M X16 (1 M X16 X4 banks)32 M X4 (8 M X4 X4 banks), 16 M X8 (4 M X8 X4 banks), 8 M X16 (2 M X16 X4 banks)64MX4(16MX4X4banks),32MX8(8MX8X4ba nks),16MX16(4MX16X4banks)128MX4(32MX4X4b anks),64MX8(16MX8X4banks),32MX16(8MX16X4 banks)256 M X4 (64 M X4 X4 banks), 128 M X8 (32 M X8 X4 banks), 64 M X16 (16 M X16 X4 banks)FEATURES Double--data--rate architecture; two datatransfersper clock cycle Bidirectional, data strobe (DQS) is transmitted/re-ceived with data, to be used in capturing data atthe receiver DQS is edge--aligned with data for READs; cen-ter--aligned with data for WRITEs Differential clock inputs (CK and CK) DLLaligns DQ andDQS transitionswithCKtransi-tions Commands entered on each positive CK edge.

5 Data and data mask referenced to both edges ofDQS Four internal banks for concurrent operation Data mask (DM) for write data Burst lengths: 2, 4, or 8 CAS Latency:2 or , DDR400 also includesCL = 3 AUTO PRECHARGE optionfor each burst access Auto Refresh and Self Refresh Modes V (SSTL_2 compatible) I/O VDDQ: + V V for DDR 200, 266, or 333+ V for DDR 400 VDD:+ V V or + V V for DDR 200, 266,or 333+ V for DDR 400 GENERAL DESCRIPTIONThe DDR SDRAM is a high--speed CMOS, dynamicrandom--access memory internally configured as aquad--bank DRAM. These devices contain the follow-ing number of bits:64 Mb has 67,108,864 bits128 Mb has 134,217,728 bits256 Mb has 268,435,456 bits512 Mb has 536,870,912 bits1 Gb has 1,073,741,824 bitsTheDDRSDRAM usesa double--data--ratearchitec-ture to achieve high--speed operation. The doubledataratearchitectureisessentially a2n prefetcharchi-tecture with an interface designed to transfer two datawords per clock cycle at the I/O pins.

6 A single read orwrite access for the DDR SDRAM effectively consistsof a single 2n--bit wide, one clock cycle data transfer atthe internal DRAM core and two corresponding n--bitwide, one--half--clock--cycle data transfers at the bidirectional data strobe (DQS) is transmitted ex-ternally, along with data, for use in data capture at thereceiver. DQS is a strobe transmitted by the DDRSDRAM during READs and by the memory controllerduring WRITEs. DQS is edge--aligned with data forREADs and center--aligned with data for DDR SDRAM operates from a differential clock(CK and CK; the crossing of CK going HIGH and CKgoing LOW will be referred to as the positive edge ofCK).Commands(addressand controlsignals) arereg-isteredateverypositiveedgeofCK. Inputdata isregis-tered on both edges of DQS, and output data is refer-enced to both edges of DQS, as well as to both edgesof and write accesses to the DDR SDRAM areburst oriented; accesses start at a selected locationand continue for a programmed number of locations ina programmed sequence.

7 Accesses begin with theregistration of an ACTIVE command, which is then fol-lowed by a READ or WRITE command. The addressbits registered coincident with the ACTIVE commandare used to select the bank and row to be address bits registered coincident with the READor WRITE command are used to select the bank DDR SDRAM provides for programmable reador write burst lengths of 2, 4 or 8 locations. An AUTOPRECHARGE function may be enabled to provide aself--timed row precharge that is initiated at the end ofthe burst with standard SDRAMs, the pipelined, multibankarchitecture of DDR SDRAMs allows for concurrentoperation, thereby providing high effective bandwidthby hiding row precharge and activation auto refresh mode is provided, along with a pow-er--saving, power--down mode. All inputs are compat-ible with the JEDEC Standard for SSTL_2. All outputsare SSTL_2, Class II VDDsupply V(nomi-nal). Eventually, all devices will migrate to a VDD sup-ply of V (nominal).

8 During this initial period of prod-uct availability, this split will be vendor and data sheet includes all features and functional-ity required for JEDEC DDR devices; options not re-quired, but listed, are noted as such. Certain vendorsmay elect to offer a superset of this specification by of-fering improved timing and/or including optional fea-tures. Users benefit from knowing that any system de-sign based on the required aspects of thisspecification are supported by all DDR SDRAM ven-dors; conversely, users seeking to use any supersetspecifications bear the responsibility to verify supportwith individual : The functionality described in, and the tim-ing specifications included in this data sheet arefor the DLL Enabled mode of : This specification defines the minimum set of requirements for JEDEC X4/X8/X16 DDR will provide individual data sheets in theirspecific format. Vendor data sheets should be con-sulted for optional features or superset Assignment Diagram, TSOP2 Assignment Table 1a TSOP2 Assignment Diagram, BGA Assignment Table 1b BGA Block Diagram -- X4/X8 Descriptions, Table 3, Burst 4, Mode Register 5, Required CAS Mode Drive , Extended Mode Register Table 1a (Commands) Table 1b (DM Operation) Table 2 (CKE) Table 3 (Current State, Same Bank)14 & Table 4 (Current State, Different Bank)16 & 7, Simplified State definitions19 & OPERATION (NOP) REGISTER 4, Row--Column Organization by 8, Activating a Specific 9, tRCD & tRRD & 10, Read 11, Read 12, Consecutive Read 13, Nonconsecutive Read 14, Random Read 15, Terminating a Read 16, Read to 17, Read to 18, Write 19, Write to Write--Max 20, Write to Write--Min 21, Write Burst -- Nom.

9 , Min., and Max tDQSS33 Fig. 22, Write To Write -- Max 23, Write To Write -- Max tDQSS, Non Consecutive 24, Random Write Cycles -- Max 25, Write To Read -- Max tDQSS, Non--Interrupting 26, Write To Read -- Max tDQSS, 27, Write To Read -- Max tDQSS,Odd Number of Data, 28, Write To Precharge -- Max tDQSS, 29, Write To Precharge -- Max tDQSS, 30, Write To Precharge -- Max tDQSS,Odd Number of Data, 31, Precharge 32, Maximum , Table Electrical Characteristics and Operating Conditions, Tab. Operating Conditions, Table Specifications and Conditions, Table 846 & 33, IDD7 Measurement Timing Waveforms48AC Electrical Characteristics (Timing Table), Table 949 & Timing Variations, DDR200, DDR266, DDR333, Table 1051 Fig. 34, Test Reference Specification Notes51 & Characteristics, DDR200, DDR266, & Derating Specifications, Tables 35 & 36, AC Overshoot/Undershoot Specification,Tables 18 & 19, 20, Clamp V--I 37, Pullup Slew Rate Test 38, Pulldown Slew Rate Test Characteristics Notes56 & 39, Full Strength Output V--I Characteristics58 & 40, Weak Output V--I Characteristics60 & SDRAM Output Driver V--I WaveformsFig.

10 41, Data Input 42, Data Output 43, Initialize and Mode Register 44, Power--Down 45, Auto Refresh 46, Self Refresh 47, Read -- Without Auto 48, Read -- Without Auto Precharge (CL= , BL=4) 69 Fig. 49, Read -- With Auto 50, Bank Read 51, Write -- Without Auto 52, Write -- With Auto 53, Bank Write 54, Write -- DM mm123456789101148474645443534 VDDNCVDDQNCDQ0 NCVDDQVSSNCVSSQNCDQ3 VDDQNCNCDQ2X4 DDR SDRAMTSOP2 CKCKE0,15161718 NCNCA11A9A81920A0A1A7A6NC,NUVDDNC,DQ1 NCNCVSSQDQSVSSQNCX8 DDR SDRAMX16 DDR SDRAM215049A2A5222324254036424143 NCVSSQ121314373938A3A4 TOP VIEWVDDVSS2627 VSSQNCVDDQNCVDDQPIN mm52515453DQ6 DQ13 NCBA0A10 VSSDQ7 DQ15NC DQ14NC DQ12DQ5 DQ11NC DQ10DQ4 DQ9NC DQ8 UDMDQ0 NCDQ1DQ1DQ2 NCDQ3DQ2DQ4 NCDQ5DQ3DQ6 NCDQ7 LDQSLDMNCCS0,RASCASWE282930313233 NCCK605958575662615564636665 DMNCVREFUDQSADDRESS ASSIGNMENT TABLED ensity Org. Bank Row AddrBank Addr64 Mb 16M X 4 4 A0 A11A0 A9BA0, BA18M X 8 4 A0 A11A0 A8BA0, BA14M X 16 4 A0 A11A0 A7BA0, BA1128 Mb 32M X 4 4 A0 A11 A0 A9, A11 BA0, BA116M X 8 4 A0 A11A0 A9BA0, BA18M X 16 4 A0 A11A0 A8BA0, BA1256 Mb 64M X 4 4 A0 A12 A0 A9, A11 BA0, BA132M X 8 4 A0 A12A0 A9BA0, BA116M X 16 4 A0 A12A0 A8BA0, BA1512 Mb 128M X 4 4 A0 A12 A0 A9,A11,A12 BA0, BA164M X 8 4 A0 A12 A0 A9, A11 BA0, BA132M X 16 4 A0 A12A0 A9BA0, BA11 Gb 256M X 4 4 A0 A13 A0 A9,A11,A12 BA0, BA1128M X 8 4 A0 A13 A0 A9,A11 BA0, BA164M X 16 4 A0 A13A0 A9BA0, BA1/AP&LSOJMS--024 FCMO--199&MO--200A13A12 CKE1,NCNCCS1,TABLE 1a.