8Gb B-die DDR4 SDRAM

1 - 1 -K4A8G045 WBRev. , Feb. 2017 SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application.

2 Or any governmental procurement to which special terms or provisions may updates or additional information about Samsung products, contact your nearest Samsung brand names, trademarks and registered trademarks belong to their respective owners. 2017 Samsung Electronics Co., All rights 8Gb B-die DDR4 SDRAM78 FBGA with Lead-Free & Halogen-Free(RoHS compliant)datasheet 2 -datasheetDDR4 SDRAMK4A8G085 WBK4A8G045 WBRev. HistoryRevision First SPEC releaseNov. Corrected typoDec. Added IDD value [1Gx8]Jan. Corrected typoMar.

3 Added values on page 11 [Table 5]27th Oct. Added information about I-temp3th Dec. Change of IDD value on page 5017th Dec. Change of Package Pinout on page 5~630th Dec. Addition of DDR4-266611th Jan. Corrected typo25th Mar. Addition of IDD value (K4A8G085WB-BCTD) on page 53~543rd Jun. Addition of DDR4-2666 (K4A4G085WB-BITD)28th Jun. Correction of typo on IDD specification12th Aug. Addition of IDD value (K4A8G045WB-BCTD) on page 53~5422th Aug. Update referring to JEDEC DDR4 datasheet Dec. Correction of Addition of Key Feature "Connectivity Test Mode (TEN) is Supported" on page 52nd Feb.

4 - 3 -datasheetDDR4 SDRAMK4A8G085 WBK4A8G045 WBRev. Of Contents8Gb B-die DDR4 SDRAM1. Ordering Information ..52. Key Package Pinout/Mechanical Dimension & Addressing .. x4 Package Pinout (Top view) : 78ball FBGA Package .. x8 Package Pinout (Top view) : 78ball FBGA Package .. FBGA Package Dimension (x4/x8) .. 84. Input/Output Functional DDR4 SDRAM Addressing ..116. Absolute Maximum Ratings .. Absolute Maximum DC DRAM Component Operating Temperature Range .. 127. AC & DC Operating AC & DC Input Measurement Levels .. AC & DC Logic Input Levels for Single-ended Signals.

5 AC and DC Input Measurement Levels: VREF AC & DC Logic Input Levels for Differential Signals .. Differential Signals Definition .. Differential Swing Requirement for Clock (CK_t - CK_c) .. Single-ended Requirements for Differential Signals .. Address, Command and Control Overshoot and Undershoot Clock Overshoot and Undershoot Specifications .. Data, strobe and Mask Overshoot and Undershoot Specifications .. Slew Rate Definitions .. Slew Rate Definitions for Differential Input Signals (CK) .. Slew Rate Definition for Single-ended Input Signals ( CMD/ADD ).

6 Differential Input Cross Point CMOS Rail to Rail Input Levels .. CMOS Rail to Rail Input Levels for RESET_n .. AC and DC Logic Input Levels for DQS Differential Signal Definition .. Differential Swing Requirements for DQS (DQS_t - DQS_c) .. Peak Voltage Calculation Method .. Differential Input Cross Point Voltage .. Differential Input Slew Rate 269. AC and DC Output Measurement Output Driver DC Electrical Alert_n Output Drive Output Driver Characteristic of Connectivity Test ( CT ) Mode .. Single-ended AC & DC Output Differential AC & DC Output Single-ended Output Slew Rate.

7 Differential Output Slew Rate .. Single-ended AC & DC Output Levels of Connectivity Test Mode .. Test Load for Connectivity Test Mode Timing .. 3310. Speed Bin .. Speed Bin Table Note .. 3911. IDD and IDDQ Specification Parameters and Test Conditions .. IDD, IPP and IDDQ Measurement 4012. 8Gb DDR4 SDRAM B-die IDD Specification Table ..5513. Input/Output Capacitance ..5714. Electrical Characteristics & AC Timing .. Reference Load for AC Timing and Output Slew Rate .. tREFI .. 59- 4 -datasheetDDR4 SDRAMK4A8G085 WBK4A8G045 WBRev. Clock Specification.

8 Definition for tCK(abs) .. Definition for tCK(avg) .. Definition for tCH(avg) and tCL(avg) .. Definition for tERR(nper) .. Timing Parameters by Speed Grade .. Rounding Algorithms .. The DQ Input Receiver Compliance Mask for Voltage and Timing .. DDR4 Function Matrix .. 72- 5 -datasheetDDR4 SDRAMK4A8G085 WBK4A8G045 WBRev. Ordering Information[ Table 1 ] Samsung 8Gb DDR4 B-die Ordering Information TableNOTE : 1. Speed bin is in order of CL-tRCD-tRP. 2. Backward compatible to lower frequency 3. 13th digit stands for below. "C" : Commercial temp/Normal power "I" : Industrial temp/Normal power2.

9 Key Features[ Table 2 ] 8Gb DDR4 B-die Speed BinsOrganizationDDR4-2133 (15-15-15)DDR4-2400 (17-17-17)2 DDR4-2666 (19-19-19)2 Package2Gx4K4A8G045WB-BCPBK4A8G045WB-BCR CK4A8G045WB-BCTD78 FBGA1Gx8K4A8G085WB-BCPBK4A8G085WB-BCRCK4 A8G085WB-BCTD78 FBGA1Gx8K4A8G085WB-BIPBK4A8G085WB-BIRCK4 A8G085WB-BITD78 FBGAS peedDDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 Unit11-11-1113-13-1315-15-1517-17-1719-1 9-19tCK(min) Latency1113151719nCKtRCD(min) (min) (min)3534333232nstRC(min) JEDEC standard ( ~ ) VDDQ = ( ~ ) 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067 MHz fCK for 2133Mb/sec/pin, 1200 MHz fCK for 2400Mb/sec/pin, 1333 MHz fCK for 2666Mb/sec/pin 16 Banks (4 Bank Groups) Programmable CAS Latency (posted CAS): 10,11,12,13,14,15,16,17,18,19,20 Programmable Additive Latency: 0, CL-2 or CL-1 clock Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600), 10,12 (DDR4-1866),11,14 (DDR4-2133),12,16 (DDR4-2400) and 14,18 (DDR4-2666) 8-bit pre-fetch Burst Length.

10 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] Bi-directional Differential Data- strobe Internal (self) calibration: Internal self calibration through ZQ pin (RZQ: 240 ohm 1%) On Die Termination using ODT pin Average Refresh Period at lower than TCASE 85 C, at 85 C < TCASE < 95 C Support Industrial Temp (-40 95 C) - tREFI at -40 C TCASE 85 C - tREFI at 85 C < TCASE 95 C Connectivity Test Mode (TEN) is Supported Asynchronous Reset Package.