A Brief Introduction to SystemVerilog

1 Spring 2015 :: CSE 502 Computer ArchitectureA BriefIntroduction to SystemVerilogInstructor: Nima Honarmand(Slides adapted from Prof. Milder sESE-507 course)Spring 2015 :: CSE 502 Computer ArchitectureFirst Things First Assume you are familiar with the basics of digital logic design If not, you can read Appendix A of Hamacheret al. SystemVerilogis a superset of another HDL: Verilog Familiarity with Verilog (or even VHDL) helps a lot Useful SystemVerilogresources and tutorials on the course project web page Including a link to a good Verilog tutorial Spring 2015 :: CSE 502 Computer ArchitectureHardware Description Languages Used for a variety of purposes in hardware design High-level behavioral modeling Register Transfer Level (RTL) behavioral modeling Gate and transistor level netlists timing models for timing simulation Design verification and testbenchdevelopment.

2 Many different features to accommodate all of these We focus on RTL modeling for the course project Much simpler than designing with gates Still, helps you think like a hardware designerSpring 2015 :: CSE 502 Computer ArchitectureHDLs vs. Programming Languages Have syntactically similar constructs: Data types, variables, assignments, if statements, loops, .. But very different mentality and semantic model: everything runs in parallel, unless specified otherwise Statement model hardware Hardware is inherently parallel Software programs are composed of subroutines(mostly) Subroutines calleach other when in a callee, the caller s execution is paused Hardware descriptions are composed of modules(mostly) A hierarchyof modules connectedto each other Modules are active at the same timeSpring 2015 :: CSE 502 Computer ArchitectureModules The basic building block in SystemVerilog Interfaces with outside using ports Ports are either inputor output(for now)5modulemymodule(a, b, c, f);outputf;inputa, b, c;// Description goes hereendmodule// alternativelymodulemymodule(input a, b, c, output f).

3 // Description goes hereendmoduleall ports declared heredeclare whichports are inputs,which are outputsmodule nameSpring 2015 :: CSE 502 Computer ArchitectureModule Instantiation You can instantiate your own modules or pre-defined gates Always inside another module Predefined: and, nand, or, nor, xor, xnor for these gates, port order is (output, input(s)) For your modules, port order is however you defined it 6modulemymodule(a, b, c, f);outputf;inputa, b, c;module_nameinst_name(port_connections) ; endmodulename ofmodule toinstantiatename ofinstanceconnect the portsSpring 2015 :: CSE 502 Computer ArchitectureConnecting Ports (By Order or Name) In module instantiation, can specify port connections byname orby order7modulemod1(inputa, b, outputf);// ..endmodule// by ordermodulemod2(inputc, d, outputg);mod1 i0(c, d, g);endmodule// by namemodulemod3(inputc, d, outputg); mod1 i0(.)

4 F(g), .b(d), .a(c));endmoduleAdvice: Useby-nameconnections(where possible)Spring 2015 :: CSE 502 Computer ArchitectureCombinational Logic DescriptionSpring 2015 :: CSE 502 Computer ArchitectureStructural Design Example: multiplexor Output equals an input Which one depends on sel modulemux(a, b, sel, f);outputf;inputa, b, sel;logicc, d, not_sel;notgate0(not_sel, sel);andgate1(c, a, not_sel);andgate2(d, b, sel);orgate3(f, c, d);endmoduledatatypefor describing logical valueBuilt-in gates:port order is:output, input(s)Spring 2015 :: CSE 502 Computer ArchitectureContinuous Assignment Specify logic behaviorallyby writing an expression to show how the signals are related to each other. assignstatement10modulemux2(a, b, sel, f);outputf;inputa, b, sel;logicc, d;assignc = a assignd = b assignf = c | d;// or alternativelyassign f = sel?

5 B : a;endmodulecdSpring 2015 :: CSE 502 Computer ArchitectureCombinational Procedural Block Can use always_combprocedural block to describe combinational logic using a series of sequential statementsmodulemymodule(a, b, c, f);outputf;inputa, b, c;always_combbegin// Combinational logic// described// inC-like syntaxendendmodule All always_combblocks are independent and parallel to each otherSpring 2015 :: CSE 502 Computer ArchitectureProcedural Behavioral Mux Descriptionmodulemux3(a, b, sel, f);outputlogicf;inputa, b, sel;always_combbeginif(sel== 0) beginf = a;endelsebeginf = b;endendendmoduleImportant: for behavior to be combinational, every output (f) must be assigned in all possible control pathsWhy? Otherwise, would be a latchand not combinational we are going to drive f this way, need to declare it as logicSpring 2015 :: CSE 502 Computer ArchitectureAccidental Latch Description This is not combinational, because for certain values of b, f must rememberits previous value.

6 This code describes a latch. (If you want a latch, you should define it using always_latch)module bad(a, b, f);output logic f;input a, b;always_combbeginif (b== 1) beginf = a;endendendmoduleSpring 2015 :: CSE 502 Computer ArchitectureMultiply-Assigned Values Both of these blocks execute concurrently So what is the value of b?We don t know!Don t do this!modulebad2(..);..always_combbeginb = .. something ..endalways_combbeginb = .. something else ..endendmoduleSpring 2015 :: CSE 502 Computer ArchitectureMulti-Bit Values Can define inputs, outputs, or logic with multiple bitsmodule mux4(a, b, sel, f);output logic [3:0] f;input [3:0] a, b;input sel;always_combbeginif (sel== 0) beginf = a;endelse beginf = b;endendendmoduleSpring 2015 :: CSE 502 Computer ArchitectureMulti-Bit Constants and Concatenation Can give constants with specified number bits In binary or hexadecimal Can concatenate with { and } Can reverse order (to index buffers left-to-right)logic[3:0] a, b, c;logicsigned[3:0] d;logic[7:0] e;logic[1:0] f;assigna = 4 b0010; // fourbits, specified in binaryassignb = 4 hC; // four bits, specified in hex == 1100assignc = 3; // == 0011assignd = -2; // 2 s complement == 1110 as bitsassigne = {a, b}; // concatenate == 0010_1100assignf = a[2 : 1].

7 // two bits from middle == 01 Spring 2015 :: CSE 502 Computer ArchitectureCase Statements and Don t-Cares module newmod(out, in0, in1, in2);input in0, in1, in2;output logic out;always_combbegincase({in0, in1, in2})3'b000: out = 1;3'b001: out = 0;3'b010: out = 0;3'b011: out = x;3'b10x: out = 1;default: out = 0;endcaseendendmoduleoutput value is undefined in this caseLast bit is a don t care --this line will be active for 100 OR 101default gives else behavior. Here active if 110 or 111 Spring 2015 :: CSE 502 Computer ArchitectureArithmetic Operators Standard arithmetic operators defined: + -* / % Many subtleties here, so be careful: four bit number + four bit number = five bit number Or just the bottom four bits arbitrary division is difficultSpring 2015 :: CSE 502 Computer ArchitectureAddition and Subtraction Be wary of overflow!

8 Use signed if you want values as 2 s complementlogic [3:0] a, b;logic [4:0] c;assign c = a + b;logic [3:0] d, e, f;assign f= d + e;4 b1000 + 4 b1000 = ..In this case, overflows to zeroFive bit output can prevent overflow:4 b1000 + 4 b1000 gives 5 b10000logicsigned[3:0] g, h, i;logicsigned[4:0] j;assigng = 4 b0001; // == 1assignh = 4 b0111; // == 7assigni = g h; assignj = g h;i== 4 b1010 == -6j == 5 b11010 == -6 Spring 2015 :: CSE 502 Computer ArchitectureMultiplication Multiply k bit number with m bit number How many bits does the result have? If you use fewer bits in your code Gets least significant bits of the productk+mlogicsigned[3:0] a, b;logicsigned[7:0] c;assigna = 4'b1110; // -2assignb = 4'b0111; // 7assignc = a*b;c= 8 b1111_0010 == -14logicsigned[3:0] a, b, d;assigna = 4'b1110; // -2assignb = 4'b0111; // 7assignd = a*b;d = 4 0010 == 2 Underflow!

9 Spring 2015 :: CSE 502 Computer ArchitectureSequential Logic DescriptionSpring 2015 :: CSE 502 Computer ArchitectureSequential Design Everything so far was purely combinational Stateless What about sequentialsystems? flip-flops, registers, finite state machines New constructs always_ff@(posedgeclk, ..) non-blocking assignment <=Spring 2015 :: CSE 502 Computer ArchitectureEdge-Triggered Events Variant of alwaysblock called always_ff Indicates that block will be sequential logic (flip flops) Procedural block occurs only on a signal s edge @(posedgeclk, negedgereset_n) begin// This procedure will be executed// anytime clkgoes from 0 to 1// or anytime reset_ngoes from 1 to 0endSpring 2015 :: CSE 502 Computer ArchitectureFlip Flops (1/3) q remembers what d was at the last clock edge One bit of memory Without reset:moduleflipflop(d, q, clk);inputd, clk;outputlogicq;always_ff@(posedgeclk) beginq <= d;endendmoduleSpring 2015 :: CSE 502 Computer ArchitectureFlip Flops (2/3) Asynchronous reset:moduleflipflop_asyncr(d, q, clk, rst_n);inputd, clk, rst_n;outputlogicq;always_ff@(posedgeclk , negedgerst_n) beginif(rst_n== 0)q <= 0.

10 Else q <= d;endendmoduleSpring 2015 :: CSE 502 Computer ArchitectureFlip Flops (3/3) Synchronous reset:moduleflipflop_syncr(d, q, clk, rst_n);inputd, clk, rst_n;outputlogicq;always_ff@(posedgeclk ) beginif(rst_n== 0)q <= 0;else q <= d;endendmoduleSpring 2015 :: CSE 502 Computer ArchitectureMulti-Bit Flip Flopmoduleflipflop_asyncr(d, q, clk, rst_n);input[15:0] d;inputclk, rst_n;outputlogic[15:0] q;always_ff@(posedgeclk, negedgerst_n) beginif(rst_n== 0)q <= 0;else q <= d;endendmoduleSpring 2015 :: CSE 502 Computer ArchitectureDigression: Module Parameters Parameters allow modules to be easily changed Instantiate and set parameter:modulemy_flipflop(d, q, clk, rst_n);parameterWIDTH=16;input[WIDTH-1:0 ] d;inputclk, rst_n;outputlogic[WIDTH-1:0] q;..endmodulemy_flipflop#(12) f0(d, q, clk, rst_n);my_flipflopf0(d, q, clk, rst_n);default value set to 16uses default valuechanges parameter to12 for this instanceSpring 2015 :: CSE 502 Computer ArchitectureNon-Blocking Assignment a <= b; <=is the non-blocking assignment operator All left-hand side values take new values concurrently This models synchronous logic!