- Advanced Organic Technology for 2.5D Interposer

1 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 APX( Advanced Package X) - Advanced Organic Technologyfor InterposerMitsuya IshidaKYOCERA SLC Technologies CorporationShiga Yasu Plant, Japan 2014 CPMT SeminarLatest Advances in Organic Interposers2 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida2 May 27 30, 2014 Mitsuya Ishida Benefits of APX Interposer Technology Feature of APX Cross Section Design Rule Comparison Material Property Design Rule for Impedance Control Electrical Performance Study Routing Capability/Study Reliability Test Status Surface Finish Experience Technology RoadmapAgenda / Outline / Overview3 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida3 May 27 30, 2014 Mitsuya IshidaBenefits of APX InterposerASICM emoryMemoryMemory APX features and benefits Fine pitch wiring and Small Size Via to support Interposer Plane pattern can be applied to POWER supply for lower IR Drop Z0 matchingof Line, Via.

2 And TH to 50 Smaller Signal transmission lossvs Silicon Interposer APX CTEis around 10ppm to strike a balance between 1stand 2ndassembly High stiffnessby using high Young Modulus and Low CTE core for easy handling and assembly Open/short testcan be done before APX is shipped Lower Cost potentialvs Silicon Interposer or Glass interposerAPXM emoryASIC LayerBuild upAPX InterposerBuild up SubstrateMother Board4 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida4 May 27 30, 2014 Mitsuya IshidaTechnology Feature of APXS mall Build Up VIAVia Hole dia. : 20umVia Land dia. : 32um3 StackLow CTE Organic Interposer10~11 ppm (total)Fine Pitch PTHP itch : 110umHole dia. : 60umLand dia. : 80umFine Line/Space Min. Line Width : 6umMin.

3 Space : 6umFine Line/Space on Core (FC1/BC1)Min. Line Width : 20umMin. Space : 20umMax. Stack Up : 5-2-5 Advanced Build-up MaterialUltra-Thin : 8umLow Loss Tangent : FC3FC4 TSMCoreFC5BC1BC2 BC3BC4 BSMBC5 Micro bump pitch Min. 40um (experienced)Min. 50um (a line escape between vias)6um6um32um5 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida5 May 27 30, 2014 Mitsuya IshidaCross Section of APX 5-2-5 Structure6 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida6 May 27 30, 2014 Mitsuya IshidaDesign rule ComparisonABF Build Up(most Advanced )APXMin. Line Width (um)96 Min. Space (um)126 Via Hole Diameter (um)6520 Via Land Diameter (um)8532 Max. number of Via Stack53 Build up Layer Thickness (um)(2ndor above B/U Layer )308 Max.

4 Build up layer115 Max. Layer Count24(11-2-11)12(5-2-5)PTH Pitch (um)150110 Cross section for 6 m Line / 6 m Space7 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida7 May 27 30, 2014 Mitsuya IshidaMaterial propertyItemABFAPXGX-13GZ-41 Build Up (ZS-100)( Measured by KST with 10umt film )CORE(Supplier s Catalogue Value)Loss 1 MHZ/1 GHz 1 MHZ/1 GHz ( ) (1 GHz)Dielectric 1 MHZ/1 GHz 1 MHZ/1 GHz / ( ) (1 GHz)CTE x-yTMA(ppm/degC)46(25-150degC)20(25-150d egC)28(30-100degC)4( 1)CTE zTMA(ppm/degC)47(25-150degC)20(25-150deg C)28(30-100degC)12( 1)TgTMA degC)156171150255(by DMA)Young (@30degC)8 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida8 May 27 30, 2014 Mitsuya IshidaDesign Rule for Impedance Control by APXS ingle end Differential pairMicro strip lineLW = Z0 =50 ohmSP = Zdiff =100 ohmLW = Z0 =50 ohmSP = Zdiff =100 ohmSingle end Differential pairStrip lineSingle end86SP18 LWLWD ifferential pairSP286LW8 SPZ0 =50 ohmZdiff =100 ohm1414C1 end Differential pairStrip lineLW =10um SP= =50 ohmLW=9um SP1 =21um SP2=16umZdiff =100 ohm9 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida9 May 27 30, 2014 Mitsuya Ishida1%2%3%4%5%6%7%8%9%10%0 5 10 15 20 25 30 35 40 45 50 55 60 Backward crosstalk (%)SP (um)

5 APXC urrent<1/31/10 Electrical Performance StudyCross Talk Noise ComparisonLoop Inductance ComparisonLoop Inductance Simulation ResultCurrent Build (Zo=50-ohm)APX28153333 SPSingle-ended (Zo=50-ohm)1k 10k 100k 1M 10M 100M 1G frequency, Hz1198765432 Loop Inductance, pHCurrent B/U DesignAPX Design1/3 Current Build UpSP8 Cross talk noise Simulation Result10 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida10 May 27 30, 2014 Mitsuya IshidaAPX Routing Capability Study for PackageVia structure(4-2-4, 5-2-5)TSV (8 m)FV4 (8 m)FV3 (8 m)50um pitch FCA (WB-DRAM)Wiring between Pads1 Line between padsPad dia. 32 mL / S = 6 m / 6 mFV2 (8 m)50 m55um pitch FCA ( HBM )1 Line between padsVia structure(5-2-5)TSV (8 m)FV4 (8 m)FV3 (8 m)Wiring between PadsPad dia.

6 32 mL / S = 6 m / mFV2 (8 m)55 m120um pitch FCATSV (15 m)FV3 (15 m)FV2 (15 m)Wiring between PadsPad dia. 32 mL / S = 6 m / 6 m6 Line between viasAPX InterposerMemoryMemoryASIC LayerBuild upBuild up Substrate11 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida11 May 27 30, 2014 Mitsuya IshidaHBM Ballout Map123456789 Power SupplyRegionTESTPORT123456789I/O Signal Region(24 rows)55um25um(MicroBump Diameter)96um18 channels+MIDSTACK(220 columns)3760I/O Signal RegionHBM Overall11212 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida12 May 27 30, 2014 Mitsuya IshidaSignal Fan-out Design Study from HBMS ignals (24)Signals (24)Signals (24)Signals (24)Top FCA PAD FC5 ( Power )FC4 Signal )FC3 ( GND )FC2 ( Signal )FC1 ( Power )COREBC1 ( Power )BC2 ( Signal )BC3 ( GND )BC4 Signal BC5 Power )

7 BOTTOM BGA PAD Top FCA PAD FC5 ( Power )FC4 Signal )FC3 ( GND )FC2 ( Signal )FC1 ( Power )COREBC1 ( Power )BC2 ( Signal )BC3 ( GND )BC4 Signal BC5 Power )BOTTOM BGA PAD PTH330um136013713 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida13 May 27 30, 2014 Mitsuya IshidaSignal Fan-out Design Study ResultSIGNALVSSVDDQVDDVPPTSMFC5FC4FC3FC2 FC1I/O Signal RegionAll Signals can be fan-out !14 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida14 May 27 30, 2014 Mitsuya IshidaReliability Test StatusSubstrate Level Reliability Test StatusTest Vehicle1. 3 Stacked VIA Chain2. 6umLine width / 6um Line-to-Line -Space3. 6um Line-to VIA_Land SpaceQualification Test StatusWTC (-65/150degC; 400cycles)PassedDTC (-55/125degC; 1000cycles)PassedHAST(130degC,85%, ; 288hrs) PassedTHB (85degC,85%,5V; 1000hrs) under TestingModule Level Reliability Test StatusTest Vehicle1.

8 Dummy Chip Attached / No FCA Joint on 3 Stacked VIA ChainQualification Test StatusWTC (-65/150degC ; 400cycles)PassedDTC (-55/125degC ; 1000cycles)PassedRisk site Line-Line) 6um space :198mm/pcsTotal : 1,782mm(198x9)Risk site Line Land 6um space : 3,280pts/pcsTotal : 29,520pts(3,280x9)Risk site 3stacked via) 40um pitch : 1,044vias/pcs 50um pitch : 1,044vias/pcsTotal : 10,440vias(1,044x10)15 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida15 May 27 30, 2014 Mitsuya IshidaSurface Finish ExperienceOSPNiAu ,NiPdAuSAC(Solder)Pad Pitch> 40um> 50um> 150umPad-Pad Space> 8um> 18umGlicoat-SMD F2(PK)Entek Cu56* Reference picture* Reference picture16 IEEE 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida16 May 27 30, 2014 Mitsuya IshidaAPX Technology RoadmapCY 2013CY 2014CY 2015CY2016CY2017~3Q4Q~SubstrateCTE (ppm)10-1110-1110-1110-1110-1110-117 (target)7 (target)7 (target)Size (mm)Depend on Build up L/SDepend on Equipment<93(12/12)<70(10/10)<93(12/12)< 70(10/10)<30( 6 / 6 )<93(12/12)<70(10/10)<30( 5 / 5 )<77( 5 / 5 )<77<77 CoreCore Layer222222 Min Line/ Space (um)

9 20/2020/2020/2020/2015/1515/15 Core Thickness (um)200200200200150 or 200150 or 200 PTH Hole (um)>50>50> Pitch (um)>150>110>100>100>80>80 PTH Land (um)808080806565 Build UpBuild up of Build up Layer455333 Min. Line/ Space (um)10/ 106/ 65/ 53/ 33/ 32/ 2 Conformal V1 viaHole (um)40/3840/3833202015 Land (um)505050323225 FilledVn viaHole (um)2020151513 Land (um)3232252522 Number of Via stack033222 Update: 64thECTC Orlando, FL, USA May 27 30, 2014 Mitsuya Ishida17 May 27 30, 2014 Mitsuya Ishida