An 554: How to Read HardCopy PrimeTime Timing Reports

1 March 2010 Altera CorporationAN 554: How to Read HardCopy PrimeTime Timing March 2010AN 554: How to Read HardCopyPrimeTime Timing ReportsTheAlteraHardCopyDesignCentergene ratestimingreportsinSynopsysPrimeTimefor mat. This application note describes the different Timing report files and explainshow to interpret (STA)timingsign-offofaproject,anAltera HardCopy Design Center (HCDC) engineer generates 15 corner critical path STA Reports of thecore and I/O path with setup and hold time analysis. Each corner contains fourtiming Reports that include setup and hold time analysis for the core and I/O timingpaths. Therefore, a total of 60 Timing Reports are delivered to the designer for reviewand following example shows a Timing report structure of a PrimeTime report for atypical industrial design. The temperature ranges from 40 to 100 (fast corner, V, 40 C with parasitic extraction from thin andnarrow metal lines, thick dielectric layers) (fast corner, V, 40 C with parasitic extraction from thick andwider metal lines, thin dielectric layers) (fast corner, V, 40 C with parasitic extraction from thick andwider metal lines, thick dielectric layers) (fast corner, V, 40 C with parasitic extraction from thin andnarrower metal lines, thin dielectric layers) (fast corner, V, 40 C with parasitic extraction from expectedtypical metal lines) (slow corner, V, 40 C with parasitic extraction from thin andnarrower metal lines, thick dielectric layers) (slow corner, V, 40 C with parasitic extraction from thick andwider metal lines, thin dielectric layers) (slow corner, V, 40 C with parasitic extraction from thick andwider metal lines, thick dielectric layers)

2 (slow corner, V, 40 C with parasitic extraction from thin andnarrower metal lines, thin dielectric layers) (slow corner, V, 40 C with parasitic extraction from expectedtypical metal lines)Page 2 Core Timing PathsAN 554: How to Read HardCopy PrimeTime Timing Reports March 2010 Altera (slow corner, V, 100 C with parasitic extraction from thin andnarrower metal lines, thick dielectric layers) (slow corner, V, 100 C with parasitic extraction from thick andwider metal lines, thin dielectric layers) (slow corner, V, 100 C with parasitic extraction from thick andwider metal lines, thick dielectric layers) (slow corner, V, 100 C with parasitic extraction from thin andnarrower metal lines, thin dielectric layers) (slow corner, V, 100 C with parasitic extraction from expectedtypical metal lines)The two essential types of Timing paths in all of the Timing Reports are the I/O-registertiming and register-to-register Timing paths. For I/O-register Timing , the Timing or output delay specified by the designer, which may be adjustable by thedesigner based on actual system Timing .

3 All I/Os must be constrained. Forregister-to-register Timing , the Timing slack is constrained solely by the clock sedge-to-edge this application note, Altera assumes you have a basic understanding of SynopsysPrimeTime Timing Reports . This application note describes HardCopy ASIC-specificpin and instance names and how Timing is reported using various more information about PrimeTime Timing Reports , refer to thePrimeTime SI Timing PathsCore Timing paths are those Timing paths that are not directly going through a chipprimary port. They are the Timing paths from a sequential cell to another sequentialcell. In HardCopy ASICs, the three main types of sequential cells are registers(Dflipflops), memories, and digital signal processors (DSPs).Register-to-RegisterYou can identify the setup Timing path byPath Type: maxand the hold timingpath byPath Type: minin a PrimeTime 1is a setup Timing PathsPage 3 March 2010 Altera CorporationAN 554: How to Read HardCopy PrimeTime Timing ReportsExample 1shows a Timing path starting from the clockCLKpin of flipflopmodem/qr_tmp, going through itsQpin, two buffer cells, and ending at the datainputDpin of another flipflop, HardCopy ASICs, you can identify a flipflop by its cell typeDFF_*, and pinsCLK,Q, andD.

4 You can identify a buffer instance by its cell typeBUF_D*. If the name of abuffer instance contains theASTstring for example,modem/qr_tmp_ASTfhInst7779 it is typically a buffer inserted by the SynopsysAstro tool. If the name of a buffer instance has a patternlcell_comb* for example,lcell_comb6052 it is a buffer inserted by the Quartus II HCDC uses a Synopsys IC Compiler during the backend implementation;therefore, the name of the instance contains theicc_Placestring for example,icc_Place_6937/OUT (BUF_D6)is a buffer inserted by the Synopsys IC typical symbols shown in a PrimeTime report are defined as follows: & after an incremental delay number shows that the delay number is calculatedwith Resistor-Capacitor (RC) network back-annotation. * for Standard Delay Format (SDF) back-annotation + for lumped RC H for hybrid annotationExample Timing Example(Note 1)Note toExample 1:(1) This is a typical register-to-register Timing path for setup 4 Core Timing PathsAN 554: How to Read HardCopy PrimeTime Timing Reports March 2010 Altera Corporation r in the path column for the rising edge of the signal f in the path column for the falling edge of the signalMost Timing Reports usensfor the time unit.

5 However, you can use the PrimeTimecommandreport_unitstoreportallt heunits,suchascapacitance,resistance,tim e,and voltage units used by the network delay is the delay from the clock port to the register clock pin. Forphase-lockedloop(PLL)clocksinnormalco mpensationmode,thepropagationdelayis fully compensated and the clock network delay is expected to be withoutskew. Skew is caused by the difference in the clock path delay of registers driven bythe same 1shows the register-to-register Timing diagram of the Timing path shown inExample Timing Diagram for Example ..073 + . |altpll|clk[2]Core Timing PathsPage 5 March 2010 Altera CorporationAN 554: How to Read HardCopy PrimeTime Timing ReportsTo show how the clock network delays and are calculated by PrimeTime ,thereport_timing -path full_clock_expandedoption is used to expand thetiming path shown inFigure 1, resulting in the Timing path shown inExample 2andExample Network Delay and Calculations in the Timing Path for Figure 1 (part 1)Page 6 Core Timing PathsAN 554: How to Read HardCopy PrimeTime Timing Reports March 2010 Altera CorporationAs shown inExample 2andExample 3, the source clock CLKIN comes into the chipfrom theclkinport with latency CLKIN goes through the clock I/O instancepin_clkinand four clock control/mux blocks, with a propagation delay of Itthen goes into the PLL through thepll_pll/RCLKPIN0checkpin1pin and gets outof the PLL through thepll_pll/CCLK2pin.

6 A negative delay of is annotatedas PLL compensation. This number is calculated by the Quartus II software andobtained from the constraint Tcl script (.tcl)file. After the PLL, the clock propagatesthrough a series of clock control muxes or clock buffers, before arriving at theflipflop s clock pinmodem/qr_tmp/CLKwith a delay of This number is theclock network delay for the launching the capture clock, the clock path shares the same path as the launching clock untilthe clock bufferXM0011A_RCLK_10_R34_Q4. From there, the capture clock goes todifferent clock branches. The clock eventually arrives at the capture register clockmodem/qr/CLKpin with a clock network delay of = Network Delay and Calculations in the Timing Path for Figure 1 (part 2)Core Timing PathsPage 7 March 2010 Altera CorporationAN 554: How to Read HardCopy PrimeTime Timing ReportsThe hold Timing for theExample 1timing path is shown inExample Timing Path for Example 1 Page 8 Core Timing PathsAN 554: How to Read HardCopy PrimeTime Timing Reports March 2010 Altera CorporationRegister-to-Memory Timing PathExample 5shows the Timing path for 5shows a Timing path starting from the clock pinCLKof flipflopileavedata[4], going through itsQpin, a delay cell, three buffers, and ending atdata input pinDINA17of memory instanceram2.

7 The capture clock pin can identify the launching flipflop by the cell typeDFF_*and Timing Path(Note 1)Note toExample 5:(1) This is a typical register-to-memory Timing Timing PathsPage 9 March 2010 Altera CorporationAN 554: How to Read HardCopy PrimeTime Timing ReportsMemory-to-Register Timing PathExample 6shows the Timing path for 6shows a Timing path starting from clock pinE_CLKBof memory instanceram129, going through its output pinEABOUT_05, and ending at the data input pinDof flipflop instancedatouthdly[3]. The capture clock pin ofdatouthdly[3] can identify the launching memory by the nameram*and by its cell typeC9250*.Example Timing Path(Note 1)Note toExample 6:(1) This is a typical memory-to-register Timing 10 Core Timing PathsAN 554: How to Read HardCopy PrimeTime Timing Reports March 2010 Altera CorporationRegister-to-DSP Timing PathExample 7shows the Timing path for 7shows a Timing path starting from the clock pinCLKof flipflopmodem/multbgoing through itsQpin, two combinational logic cells (typeCHLE_*and typeADDER_*), two buffers, and ending at data input pinINBX0of DSP instancemac_mult180647(typeC9550*).

8 The capture clock pin can identify the launching flipflop by the cell typeDFF_*and Timing PathNote toExample 7:(1) This is a typical register-to-DSP Timing Timing PathsPage 11 March 2010 Altera CorporationAN 554: How to Read HardCopy PrimeTime Timing ReportsDSP-to-Register Timing PathExample 8shows the Timing path for 8shows a Timing path starting from clock pinCLK_Aof DSP blockmac_mult180647, going through its out pinMAC_OUTB34, six combinational logiccells and buffers, and ending at the data input pinDof flipflop instancemodem/out12. The capture clock pin can identify the launching DSP by the namemac_mult*and by its cell typeC9550*.Example Timing Path(Note 1)Note toExample 8:(1) This is a typical DSP-to-register Timing 12I/O Timing PathAN 554: How to Read HardCopy PrimeTime Timing Reports March 2010 Altera CorporationI/O Timing PathI/O Timing paths are those Timing paths going through any chip primary input port orprimary output port. For illustration purposes, this application note divides I/Otiming paths into two categories: typical I/O and I/OThe following sections describe input and output I/O I/O Timing PathExample 9shows the input I/O Timing path to an I/O 9, the input I/O port name given by the designer isexrw; the capture I/Oregister name in the HardCopy ASIC ispin_exrw; the registerDpin name isDATOVR; and the registerCLKpin name HardCopy ASIC cell typeC67002_0000000F90C1040298200000108_V 33_LVTTL designates that it is LVTTL type of I/O.

9 The master I/O type given by Altera isC67002, while0000000F90C1040298200000108is the specific configuration bit settings forC67002in this I/O Timing Path to an I/O Register(Note 1)Note toExample 9:(1) This is a typical I/O Timing path to an I/O Timing PathPage 13 March 2010 Altera CorporationAN 554: How to Read HardCopy PrimeTime Timing ReportsPrimeTime takes ns as input external delay inExample 9for its timingcalculation. The number comes from the constraint SDC file, in which the designerspecifies a ns input delay:set_input_delay -add_delay -max -clock [get_clocks {EXCLK}] [get_ports exrw]Example 10shows the input I/O Timing path to a core 10, the input I/O port name isdischg. It is clocked by travels out of I/O instancepin_dischgthrough theCDATA0 INpin, thentravels through bufferpin_dischgASTfhInst10846and delay cellpin_dischgASTfhInst8085, then travels through a combinational logic celllcell_comb8533, two more delay cellsU109andU115, and ends at theDpin of thecore I/O Timing Path to a Core RegisterPage 14I/O Timing PathAN 554: How to Read HardCopy PrimeTime Timing Reports March 2010 Altera CorporationThe following cell types are used in HardCopy ASICs: DEL_* a delay cell that is mainly used for hold time fixing BUF_* a data buffer that is mainly used for buffering data delay to meet setuptiming CHLE_* an Altera proprietary logic element that is typically used to constructcombinational logic DFF_* shows the instance is aDflipflopThe engineering change order (ECO)-inserted buffer or delay cells typically have aname pattern ofU[0-9999].

10 For example, I/O TimingExample 11shows the output I/O Timing path from an I/O 11,thelaunchingI/Oregisternameispin_pn_c nt1;theregisterCLKpinname isCLKOUT; and the output I/O port name given by the designer output external delay comes from the designer constraint:set_output_delay -add_delay -max -clock [get_clocks{in_lvds_mode}] [ get_ports pn_cnt1 ]Example Timing Path from an I/O RegisterI/O Timing PathPage 15 March 2010 Altera CorporationAN 554: How to Read HardCopy PrimeTime Timing ReportsExample 12shows the output I/O Timing path from a core 12, the launching core register name isrl_inv_rep_ff. Data travels outof the core register at theQpin, through two buffers, goes into I/Opin_pn_rl_invert, and finally arrives at the output I/O designer used the following constraint:set_output_delay -add_delay -max -clock [get_clocks{in_lvds_mode}] [get_ports pn_rl_invert]Example I/O Timing Path from a Core RegisterPage 16I/O Timing PathAN 554: How to Read HardCopy PrimeTime Timing Reports March 2010 Altera CorporationBidir I/O TimingFor the bidir I/O port, there is both a data input Timing path and a data output timingpath.