ARMv8-A/-R Debugger - Lauterbach

1 ARMv8-A/-R Debugger 1 1989-2018 Lauterbach GmbHARMv8-A/-R Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents .. ICD In-Circuit Debugger .. Processor Architecture Manuals .. ARM/CORTEX/XSCALE .. ARMv8-A/-R Debugger ..1 History ..7 Warning ..8 Introduction ..9 Brief Overview of Documents for New Users9 Demo and Start-up Scripts10 Quick Start of the JTAG Debugger ..12 Troubleshooting ..16 Communication between Debugger and Processor cannot be established16 FAQ ..17 Cortex-A/R ( armv8 , 32/64-bit)17 Trace Extensions19 Quick Start for Multicore Debugging.

2 20 SMP Debugging - Quick Start21 1. How to Debug a System with Multiple Identical Cores21 2. Set up the SMP Debug Scenario22 3. Enter Debug Mode23 4. Switch Debug View between Cores23 5. Write a Start-up Script Summary23 AMP Debugging - Quick Start24 1. How to Debug a System with Multiple Heterogenous Cores24 2. Starting the TRACE32 GUIs24 3. Master-Slave Concept25 4. Setting up the Multicore Environment25 5. Synchronized Go / Step / Break26 6. Write a Start-up Script Summary26 ARM Specific Implementations.

3 27 AArch Mode Support27 ARMv8-A/-R Debugger 2 1989-2018 Lauterbach GmbH AArch64 and AArch32 Debugging27 AArch64 and AArch32 Switching28 TrustZone Technology30 AArch64 Secure Model30 AArch32 Secure Model31 Debug Permission31 Checking Debug Permission31 Checking Secure State32 Changing the Secure State from within TRACE3232 AArch64 System Registers Access33 AArch32 Coprocessor Registers Access33 Accessing Cache and TLB Contents33 Breakpoints and Vector Catch Register33 Breakpoints and Secure Modes33 Debugger Setup34 Consequence for Debugging35 Requirements for the Target Software35 MP35 Breakpoints36 Software Breakpoints36 On-chip Breakpoints for Instructions36 On-chip Breakpoints for Data36 Example for Standard Breakpoints37 Secure, Non-Secure, Hypervisor Breakpoints38 Example for ETM Stopping Breakpoints42 Access Classes43 System Registers (AArch64 Mode)

4 51 Coprocessors (AArch32 Mode)53 Accessing Memory at Run-time56 Semihosting60 AArch64 HLT Emulation Mode61 AArch64 DCC Communication Mode (DCC = Debug Communication Channel)62 AArch32 SVC (SWI) Emulation Mode63 AArch32 DCC Communication Mode (DCC = Debug Communication Channel)64 Virtual Terminal66 Large Physical Address Extension (LPAE)67 Consequence for Debugging67 Virtualization Extension, Hypervisor68 Consequence for Debugging68 Debug Field69 Run Mode69 Runtime Measurement70 ARMv8-A/-R Debugger 3 1989-2018 Lauterbach GmbH Trigger70 ARM specific SYStem Commands.

5 71 Debugger about core clock71 target configuration71 Debugger according to target topology72 <parameters> describing the DebugPort 79 <parameters> describing the JTAG scan chain and signal behavior84 <parameters> describing a system level TAP Multitap 88 <parameters> configuring a CoreSight Debug Access Port DAP 90 <parameters> describing debug and trace Components 94 <parameters> which are Deprecated 104 GICDG eneric Interrupt Controller Distributor (GIC)109 GICRG eneric Interrupt Controller Redistributor112 GICCG eneric Interrupt Controller physical CPU interface113 GICHG eneric Interrupt Controller virtual interface control114 GICVG eneric Interrupt Controller virtual CPU interface115 SMMUI nternal use116 the used CPU118 memory access (intrusive)

6 119 JTAG frequency120 the JTAG port121 memory access122 the communication with the target123 setup125 Address32 Define address format display125 AHBHPROTS elect AHB-AP HPROT bits125 AXIACEE nableACE enable flag of the AXI-AP126 AXICACHEFLAGSS elect AXI-AP CACHE bits126 AXIHPROTS elect AXI-AP HPROT bits127 BreakOSAllow break during OS-unlock128 CFLUSHFLUSH the cache before step/go129 CLTAPKEYSet key values for CLTAP operation129 CoreSightRESetAssert CPU reset via CTRL/STAT129 DAPDBGPWRUPREQF orce debug power in DAP130 DAP2 DBGPWRUPREQF orce debug power in DAP2131 DAPNOIRCHECKNo DAP instruction register check131 DAPREMAPR earrange DAP memory map132 DAPSYSPWRUPREQF orce system power in DAP132 DAP2 SYSPWRUPREQF orce system power in DAP2133 DBGSPRUse Debugger view for SPR access133 DBGUNLOCKU nlock debug register via OSLAR134 DCacheMaintenanceData cache maintenance strategy134 DEBUGPORTO ptionsOptions for debug port handling134 ARMv8-A/-R Debugger 4 1989-2018 Lauterbach GmbH

7 DIAGA ctivate more log messages135 DUALPORTI mplicitly use run-time memory access135 DisModeDefine disassembler mode136 EnResetAllow the Debugger to drive nRESET (nSRST)137 eXclusiveMONitorSupport for exclusive monitors137 HRCWOVerRideEnable override mechanism137 ICacheMaintenanceI-Cache maintenance strategy138 IMASKASMD isable interrupts while single stepping138 IMASKHLLD isable interrupts while HLL single stepping139 INTDISD isable all interrupts139 MACHINESPACESA ddress extension for guest OSes140 MEMORYHPROTS elect memory-AP HPROT bits140 MemStatusCheckCheck status bits during memory access141 MMUSPACESS eparate address spaces by space IDs141 NOMAUse alternative memory

8 Access142 NoPRCRR esetDisable warm reset via PRCR143 OSUnlockCatchUse the 'OS Unlock Catch' debug event143 OVERLAYE nable overlay support144 PALLADIUME xtend Debugger timeout144 PWRDWNA llow power-down mode145 PANO verwrite setting145 PWRREQR equest core power145 ResBreakHalt the core after reset146 ResetDetectionChoose method to detect a target reset147 nRESET/nSRST on JTAG connector147 RESetREGisterGeneric software reset148 RisingTDOT arget outputs TDO on rising edge148 SLaVeSOFTRESetAllow soft reset of slave cores149 SMPM ultipleCallSend start event to each SMP core149 SOFTLONGUse 32-bit access to set breakpoint149 SOFTQUADUse 64-bit access to set breakpoint149 STEPSOFTUse software breakpoints for ASM stepping150 SOFTWORDUse 16-bit access to set breakpoint150 TURBOD isable cache maintenance during memory access150 SYStem window151 SYSPWRUPREQF orce system power151 TRSTA llow Debugger to drive TRST152 WaitIDCODEIDCODE polling after deasserting reset152 WaitResetWait with JTAG

9 Activities after deasserting reset153 ZoneSPACESE nable symbol management for ARM zones154 Overview of Debugging with Zones155 Operation System Support - Defining a Zone-specific OS Awareness158 ZYNQJTAGINDEPENDENTC onfigure JTAG cascading160 ARMv8-A/-R Debugger 5 1989-2018 Lauterbach GmbH ARM specific Benchmarking Commands ..161 BMC.<counter>.CountEL<x>Select exception level events to be counted161 ARM specific TrOnchip Commands ..163 on-chip breakpoint/trace filter by ASID164 on-chip breakpoint/trace filter by zone165 context ID comparison166 extension of address range of breakpoint166 breakpoint or watchpoint from Debugger usage167 on-chip trigger to default state168 bits in the vector catch register168 breakpoints on scalar variables171 on-chip trigger window172 Cache Analysis and Maintenance.

10 173 CPU specific MMU Commands ..175 wise display of MMU translation table175 display of MMU translation table186 MMU table from CPU188 TRACE32 Support by CPU Type190 CPU specific SMMU Commands ..191 SMMUH ardware system MMU (SMMU)191 a new hardware system MMU195 an SMMU196 registers of an SMMU197 registers of context bank198 global registers of SMMU199 registers of an SMRG200 all SMMU definitions201 security state determination table202 to stream map table entries204 context bank registers205 display of SMMU page table207 the page table entries