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General Commands Reference Guide D - Lauterbach

General Commands Reference Guide D 1 1989-2017 Lauterbach GmbHGeneral Commands Reference Guide DTRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents .. General Commands .. General Commands Reference Guide D ..1 History ..6 Data ..7 DataMemory access7 Memory Access by the TRACE32 Debugger7 Access Procedures7 Memory Access by TRACE32-ICE, TRACE32-FIRE9 Access Procedures9 Memory Classes10 Keywords for <width>11 Functions12 memory allocation analysis13 assembler18 buffer descriptor table19 cache/memory bandwidth20 linked list24 in linked list27 the TRACE32 virtual memory (VM.)

General Commands Reference Guide D 1 ©1989-2018 Lauterbach GmbH General Commands Reference Guide D TRACE32 Online Help TRACE32 Directory

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Transcription of General Commands Reference Guide D - Lauterbach

1 General Commands Reference Guide D 1 1989-2017 Lauterbach GmbHGeneral Commands Reference Guide DTRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents .. General Commands .. General Commands Reference Guide D ..1 History ..6 Data ..7 DataMemory access7 Memory Access by the TRACE32 Debugger7 Access Procedures7 Memory Access by TRACE32-ICE, TRACE32-FIRE9 Access Procedures9 Memory Classes10 Keywords for <width>11 Functions12 memory allocation analysis13 assembler18 buffer descriptor table19 cache/memory bandwidth20 linked list24 in linked list27 the TRACE32 virtual memory (VM.)

2 28 memory29 memory31 linked list of CSA entries34 memory display of arrays35 display of fast fourier transformation39 display of xy-graphs42 dump45 Format Options47 Standard Options48 Advanced Options55 data modification on program execution halt57 condition for data epilog58 core for data epilog59 data epilog off59 General Commands Reference Guide D 2 1989-2017 Lauterbach GmbH data epilog on60 all data epilogs60 the index number to the next data epilog61 epilog sequence62 data epilogs63 epilog target call64 in memory65 command on specified code type67 to address68 for string69 image data70 port73 file74 Alphabetic List of Generic Load Options75 Details on Generic Load Options80 Program Loading (TRACE32-ICE)

3 87 Format Specific Commands and Options88 ARM image file88 file89 ASAP2 file89 hex file90 octal file90 AVOCET file91 BDX file91 binary file92 BOUND file95 SDCC CDB file format95 COFF file97 COMFOR (TEKTRONIX) file98 Linux core dump file99 COSMIC file100 MS Windows crash dump file101 file102 ELF file103 EST flat binary112 EXE file112 HICROSS file113 HITECH file114 HP-64000 file115 ICOFF file116 IEEE-695 file117 INTEL-HEX file119 General Commands Reference Guide D 3 1989-2017 Lauterbach GmbH JEDEC file119 Mach-O file120 MAP file122 MCDS file122 MCOFF file123 OAT

4 File123 OMF file124 Special Requirements for Intel PL/M-86 and PL/M-51127 OMF-251 files128 special hex files128 file129 OS-9 file130 Limitations131 SDSI file131 S-Record file132 symbol file133 RENESAS SYSROF file134 TEKTRONIX file134 TEKTRONIX HEX file135 UBROF file136 VERSADOS file137 XCOFF file137 FLASHDISK support138 port139 memory with pattern140 multiple areas142 display of data value145 window147 data modification on program execution start148 PROLOG condition149 core for data prolog150 data prolog off150 data prolog on151 all data prologs151 the index number to the next data prolog152 prolog sequence153 data prologs154 PROLOG target call155 current values156 function call157 <format>Save data in file with specified format158 hex file160 General

5 Commands Reference Guide D 4 1989-2017 Lauterbach GmbH octal file161 BDX file162 binary file162 CCSDAT file163 DAB file163 EST flat binary file164 INTEL-HEX file164 OMF file165 pure HEX file165 S-record file166 memory168 sequence after setting software sequence before setting software data sequence171 data sequence172 startup condition172 startup sequence off172 startup data sequence on173 startup data sequence173 startup data sequence174 data state display175 display176 checksum176 arrays179 code for analysis181 code for analysis181 integrity test184 for memory type187 data sequence188 timer condition188 timer off189 timer on189 timer189 timer sequence190 state display191 timer target call191 period for timer192 code tags193

6 Memory cache update193 USR access193 memory195 string to PRACTICE file197 DCI ..198 General Commands Reference Guide D 5 1989-2017 Lauterbach GmbH DCID irect Connect Interface (DCI)198 DQMT race ..199 DTM ..200 DTMDTM trace sources (Data Trace Module)200 DTU ..200 DTUD ebug Trace Unit (DTU)200 Usage:(B) command only available for ICD(E) command only available for ICE(F) command only available for FIRE General Commands Reference Guide D 6 1989-2017 Lauterbach GmbHGeneral Commands Reference Guide DVersion 06-Nov-2017 History12-Jun-17 Updated illustration for the BSPLIT option of the Commands .

7 /BSPLIT and for command added. General Commands Reference Guide D 7 1989-2017 Lauterbach GmbHDataData Memory accessSee also <format> () () () () () () () () () () () Memory Access by the TRACE32 DebuggerTRACE32 debuggers operate on the memory of the target ProceduresThe following examples show typical memory access 0x1000.

8 Display a hex dump starting at; address 0x1000 %Byte 0x55; write 0x55 as a byte to the ; address ; load program from file to; the target memory General Commands Reference Guide D 8 1989-2017 Lauterbach GmbHAn access class can be used to specify memory access details. A:0x1000; display a hex dump starting at; address 0x1000, physical NC:0x1234; display a hex dump starting at; address 0x1234, non-cached L2:0x1234; display a hex dump starting at; address 0x1234, L2 cache access General Commands Reference Guide D 9 1989-2017 Lauterbach GmbHMemory Access by TRACE32-ICE, TRACE32-FIREThe TRACE32 In-Circuit Emulators feature dual-port emulation memory which can be accessed by both the emulation CPU, as well as the system control CPU.

9 The emulation CPU always reads data from memory which is assigned to it via the or command (external or internal memory). However, the dual-port function allows access to emulation memory only. Memory access to external memory or to I/O areas must always be handled via the emulation emulation memory works in parallel to external emulation memory. After write-to execution both memory areas are updated. Wait states results on the signals generated by the target ProceduresAccess procedures are selected by entering a memory class in the address field. For example, if the commandis used to represent memory in the USERDATA address space, as of address commandwill be used to represent the same address space, except that it can be accessed only directly via emulation memory, thus ensuring that memory contents are also visible during realtime EUD.

10 0x1000 Access via emulation CPUD ebug>Monitor/Emulation EmulationMemory CPUDual-portaccess>Dual-portInt/ExtEmula tionController MappingProbeTargetOn-Chip DebugInterface General Commands Reference Guide D 1 0 1989-2017 Lauterbach GmbHMemory ClassesThe available memory access classes depend on the target processor. Some classes are available at all probes:Other classes are described within the Processor Architecture Manuals, ICE Target Guides, and FIRE Target SpaceDData SpaceCAccess by the CPUED irect access to emulation memoryEPDirect access to program memoryEDDirect access to data memoryAAbsolute (Physical addressing) General Commands Reference Guide D 1 1 1989-2017 Lauterbach GmbHKeywords for <width>In the Data command group, TRACE32 provides the following keywords for <width>: [<width>] ByteWordTByteLongPByteHByteSByteQuadByte 8-bitWord16-bitT


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