MPC5xx/8xx Debugger and Trace - Lauterbach

1 MPC5xx/8xx Debugger and Trace 1 1989-2020 Lauterbach GmbHMPC5xx/8xx Debugger and Trace TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents .. ICD In-Circuit Debugger .. Processor Architecture Manuals .. PQ/MPC500 .. MPC5xx/8xx Debugger and Trace ..1 Brief Overview of Documents for New Users ..5 Warning ..6 Quick Start ..7 Target Design Requirement/Recommendations ..9 General9 RESET Configuration10 BDM Termination11 General Restrictions12 Troubleshooting13 Errors13 FAQ ..13 Configuration ..14 Breakpoints ..16 Software Breakpoints16 On-chip Breakpoints16 On-chip Breakpoints on InstructionsROM or FLASH17 On-chip Breakpoints on Read or Write Accesses17 Example for Breakpoints17 Simultaneous FLASH Programming for MPC55518 Memory Classes.

2 19 Memory Coherency MPC8xx19 Trace Extension ..20 MPC555/MPC553 Pin Multiplexing20 Troubleshooting MPC500/MPC800 RISC Trace21 Used Options for RiscTrace21 General SYStem Commands ..22 MPC5xx/8xx Debugger and Trace 2 1989-2020 Lauterbach GmbH the BDM clock speed22 Debugger according to target topology22 CPU type22 memory access (intrusive)23 control to deny stopping the target (long stop)23 control to deny spotting the target (short stop)25 memory access (non-intrusive)26 the communication with the CPU27 CPU specific SYStem Commands ..28 vocabulary for code compression28 BRKNOMSKA llow program stop in a non-recoverable state28 CCOMPE nable code compression29 CLEARBEC lear MSR[BE]

3 On step/go29 CSxxxCS setting for program flow trace29 DCREADUse DCACHE for data read30 FAILSAVES pecial error handling for debug port31 FreezePinUse alternative signal on the BDM connector31 IBUSC onfigure the show cycles for the I-BUS32 ICFLUSHF lush branch target cache before program start32 ICREADUse ICACHE for program read33 IMASKASMD isable interrupts while single stepping33 IMASKHLLD isable interrupts while HLL single stepping33 LittleEndSelection of little endian mode34 MMUSPACESE nable space IDs34 NODATAThe external data bus is not connected to trace35 NOTRAPUse alternative instruction to enter debug mode35 OVERLAYE nable overlay support36 PPCL ittleEndControl for PPC little endian36 SCRATCHS cratch for FPU access37 SIUMCRSIUMCR setting for the trace37 SLOWLOADA lternative data load algorithm37 SLOWRESETA ctivate SLOWRESET37 WATCHDOGE nable software watchdog after SYStem window38 CPU specific MMU commands.

4 39 wise display of MMU translation table39 display of MMU translation table41 MMU table from CPU42 MMU TLB entries43 MMU TLB entries43 an MMU TLB entry44 CPU specific TrOnchip Commands ..45 MPC5xx/8xx Debugger and Trace 3 1989-2020 Lauterbach GmbH range breakpoint in on-chip resource45 NEXUS Trace register control45 NEXUS Trace register control46 data selector46 counter for I-Bus watchpoint47 address for I-Bus watchpoint48 I-Bus watchpoint pin48 counter for L-Bus watchpoint49 type for L-Bus watchpoint50 selector for L-Bus watchpoint50 address for L-Bus watchpoint50 address for the L-Bus watchpoint51 L-Bus watchpoint pin52 on-chip trigger unit52 program execution at specified exception52 data compression53 filter for the trace53 the sampling to the Trace to OFF54 the sampling to the Trace to ON54

5 A trigger for the trace54 HLL breakpoint in on-chip resource54 on-chip trigger window54 BenchMarkCounter ..56 BDM Connector ..57 10 pin BDM Connector MPC500/MPC80057 Support ..58 Available Tools58 Compilers59 Target Operating Systems60 3rd-Party Tool Integrations62 Products ..64 Product Information64 Order Information64 MPC5xx/8xx Debugger and Trace 4 1989-2020 Lauterbach GmbHMPC5xx/8xx Debugger and TraceVersion 21-Feb-2020 MPC5xx/8xx Debugger and Trace 5 1989-2020 Lauterbach GmbHBrief Overview of Documents for New UsersArchitecture-independent information: Debugger Basics - Training ( ): Get familiar with the basic features of a TRACE32 Debugger . T32 Start ( ): T32 Start assists you in starting TRACE32 PowerView instances for different configurations of the Debugger .

6 T32 Start is only available for Windows. General Commands (general_ref_<x>.pdf): Alphabetic list of debug information: Processor Architecture Manuals : These manuals describe commands that are specific for the processor architecture supported by your debug cable. To access the manual for your processor architecture, proceed as follows:- Choose Help menu > Processor Architecture Manual. OS Awareness Manuals (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating system-aware debugging. The appropriate OS Awareness manual informs you how to enable the OS-aware debugging. MPC5xx/8xx Debugger and Trace 6 1989-2020 Lauterbach GmbHWarningWARNING:To prevent Debugger and target from damage it is recommended to connect or disconnect the debug cable only while the target power is for the software the debug cable from the target while the target power is the host system, the TRACE32 hardware and the debug ON the TRACE32 the TRACE32 software to load the Debugger the debug cable to the the target power your Debugger via a start-up off the target the debug cable from the the TRACE32 OFF the TRACE32 hardware.

7 MPC5xx/8xx Debugger and Trace 7 1989-2020 Lauterbach GmbHQuick StartStarting up the BDM Debugger is done by the following the device prompt B: for the TRACE32 ICD- Debugger , if the device prompt is not active after starting the TRACE32 the CPU type to load the CPU specific default CPU is the the Debugger where s FLASH/ROM on the target, this is necessary for the use of the on-chip breakpoints. On-chip breakpoints are now used, if a program or spot breakpoint is set within the specified address range. A list of all available on-chip breakpoints for your architecture can be found under On-chip debug command resets the CPU, enables the debug mode and stops the CPU at the first opfetch (reset vector). After this command is possible to access memory and the IBUS. the special function registers to prepare your target memory for program 0x100000++ IBUS NONE; No show cycles are performed.; Recommended for BDM Debugger IBUS IND; Show cycles are generated for all; indirect changes in the program flow.

8 ; Recommended if a RISC Trace or; PowerTrace module is SPR:027E %Long 0x800 MPC5xx/8xx Debugger and Trace 8 1989-2020 Lauterbach the load command depends on the file format generated by your compiler. For more information refer to Compiler. A full description of the command is given in the General Commands Reference .The start-up sequence can be automated using the script language PRACTICE. A typical start sequence is shown below. This sequence can be written to a PRACTICE script file (*.cmm, ASCII format) and executed with the command DO <file>. *) These commands open windows on the screen. The window position can be specified with the WinPOS command. Refer to the PEDIT command to write a script and to the DO command to start a ; Load ELF fileB::; Select the ICD- Debugger device; promptWinCLEAR; Delete all 0x100000++0x0fffff; Specify where s 0x563; Select the processor ; Reset the target and enter debug; ; Load the PC main; Set the PC to the function ; Open a source listing *) /SpotLight; Open the register window *) /Locals /Caller; Open the stack frame with ; local variables *) %Spotlight flags ast; Open watch window for variables *) ; Open a window for the special; function sieve; Set breakpoint to function 0x1000 /Program; Set a software breakpoint to address; 1000 (address 1000 is in RAM) 0x101000 /Program; Set an on-chip breakpoint to address.

9 101000 (address 101000 is in FLASH) MPC5xx/8xx Debugger and Trace 9 1989-2020 Lauterbach GmbHTarget Design Requirement/RecommendationsGeneral Locate the BDM connector as close as possible to the processor to minimize the capacitive influence of the line length and cross coupling of noise onto the BDM that the Debugger signal (HRESET) is connected directly to the HRESET of the processor. This will provide the ability for the Debugger to drive and sense the status of HRESET. The target design should only drive the HRESET with open collector, open drain. HRESET should not be tied to PORESET, because the Debugger drives the HRESET and DSCK to enable BDM operation. The TRACE32 internal buffer/level shifter will be supplied via the VCCS pin. Therefore it is necessary to reduce the VCCS pull-up on the target board to a value smaller 10 . MPC5xx/8xx Debugger and Trace 1 0 1989-2020 Lauterbach GmbHRESET ConfigurationAt HRESET the Hard Reset Configuration bits will be sampled.

10 Depending on the RSTCONF pin the external or the internal configuration word is multifunction I/O pins (VFLS0/1) have to be configured correctly for the debugging. Drive actively the following pins:There are two signal schemes possible to indicate the processor status to the Debugger . Option A is recommended but Option B is also supported for the BDM functionality. Option B is used as an alternative to eliminate pin conflicts. Option B is typically used if: the internal watchpoints are used the amount of signals must be reduced to a minimum the target design uses PCMCIA Port A: Using the VFLS pinsMPC800: (DBGC=[11]; DBPC=0; FRC=x)MPC500: (DBGC=[00,10]; DBPC=0; GPC=x)RSTCONFC onfiguration Word0 DATA[ ] pins1internal data default word (0x0000 0000)MPC5xxDBGC(D9,D10) and DBPC(D11)MPC8xxDBGC(D9,D10) and DBPC(D11,D12)CommentSignal NamePINPINS ignal NameCommentIPB0/IWP0/VFLS012/SRESETGND34 DSCK/TCKGND56IP_BI/IWP1/VFLS1 HRESET78 DSDI/TDIVCCS910 DSDO/TDO MPC5xx/8xx Debugger and Trace 1 1 1989-2020 Lauterbach GmbHOption B: Using the FREEZE pinMPC800: (DBGC=[11]; DBPC=0; FRC=0)MPC500: (DBGC=[00,10]; DBPC=0.)