Cadence Verilog -AMS Language Reference

1 Cadence Verilog -AMS Language Reference Product Version June 2005. 2000-2005 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. ( Cadence ) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence 's trademarks, contact the corporate legal department at the address shown above or call Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, trademark, and other laws.

2 Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence . This statement grants you permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used solely for personal, informational, and noncommercial purposes;. 2. The publication may not be modified in any way;. 3. Any copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement; and 4. Cadence reserves the right to revoke this authorization at any time, and any such use shall be discontinued immediately upon written notice from Cadence . Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence .

3 The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence 's customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in and et seq. or its successor. Cadence Verilog -AMS Language Reference Contents Preface.

4 17. Related Documents .. 18. Internet Mail Address .. 19. Typographic and Syntax Conventions .. 19. 1. Modeling Concepts .. 21. Verilog -A Language Overview .. 22. Describing a System .. 22. Analog Systems .. 23. Nodes .. 23. Conservative Systems .. 24. Signal-Flow Systems .. 24. Mixed Conservative and Signal-Flow Systems .. 25. Simulator Flow for Analog Systems .. 25. 2. Creating Modules .. 27. Overview .. 28. Declaring Modules .. 28. Declaring the Module Interface .. 31. Module Name .. 31. Ports .. 31. Parameters .. 34. Defining Module Analog Behavior .. 34. Defining Analog Behavior with Control Flow .. 36. Using Integration and Differentiation with Analog Signals .. 38. Using Internal Nodes in Modules .. 39. Using Internal Nodes in Behavioral Definitions .. 39. Using Internal Nodes in Higher Order Systems .. 40. June 2005 3 Product Version Cadence Verilog -AMS Language Reference 3.

5 Lexical Conventions .. 43. White Space .. 44. Comments .. 44. Identifiers .. 44. Ordinary Identifiers .. 45. Escaped Names .. 45. Scope Rules .. 45. Numbers .. 46. Integer Numbers .. 46. Real Numbers .. 46. Strings .. 47. 4. Data Types and Objects .. 49. Integer Numbers .. 50. Real Numbers .. 50. Converting Real Numbers to Integer Numbers .. 51. Parameters .. 51. Specifying a Parameter Type .. 52. Specifying Permissible Values .. 53. Natures .. 54. Declaring a Base Nature .. 55. Disciplines .. 57. Binding Natures with Potential and Flow .. 58. Binding Domains with Disciplines .. 59. Disciplines and Domains of Wires and Undeclared Nets .. 60. Discipline Precedence .. 60. Compatibility of Disciplines .. 60. Net Disciplines .. 63. Ground Nodes .. 65. Real Nets .. 65. Named Branches .. 66. Implicit Branches .. 67. June 2005 4 Product Version Cadence Verilog -AMS Language Reference 5.

6 Statements for the Analog Block .. 69. Assignment Statements .. 69. Procedural Assignment Statements in the Analog Block .. 70. Branch Contribution Statement .. 70. Indirect Branch Assignment Statement .. 72. Sequential Block Statement .. 73. Conditional Statement .. 74. Case Statement .. 74. Repeat Statement .. 75. While Statement .. 76. For Statement .. 76. Generate Statement .. 77. 6. Operators for Analog Blocks .. 81. Overview of Operators .. 82. Unary Operators .. 83. Unary Reduction Operators .. 83. Binary Operators .. 85. Bitwise Operators .. 88. Ternary Operator .. 89. Operator Precedence .. 90. Expression Short-Circuiting .. 90. 7. Built-In Mathematical Functions .. 91. Standard Mathematical Functions .. 92. Trigonometric and Hyperbolic Functions .. 92. Controlling How Math Domain Errors Are Handled .. 93. June 2005 5 Product Version Cadence Verilog -AMS Language Reference 8.

7 Detecting and Using Events .. 95. Detecting and Using Events .. 96. Initial_step Event .. 97. Final_step Event .. 98. Cross Event .. 99. Above Event .. 100. Timer Event .. 102. 9. Simulator Functions .. 103. Announcing Discontinuity .. 105. Bounding the Time Step .. 107. Finding When a Signal Is Zero .. 107. Querying the Simulation Environment .. 108. Obtaining the Current Simulation Time .. 109. Obtaining the Current Ambient Temperature .. 109. Obtaining the Thermal Voltage .. 110. Obtaining and Setting Signal Values .. 110. Obtaining Currents Using Out-of-Module References .. 112. Accessing Attributes .. 113. Examining Drivers .. 114. Counting the Number of Drivers .. 114. Determining the Value Contribution of a Driver .. 115. Determining the Strength of a Driver .. 115. Detecting Updates to Drivers .. 116. Analysis-Dependent Functions .. 116. Determining the Current Analysis Type.

8 116. Implementing Small-Signal AC Sources .. 118. Implementing Small-Signal Noise Sources .. 118. Generating Random Numbers .. 120. Generating Random Numbers in Specified Distributions .. 121. Uniform Distribution .. 121. Normal (Gaussian) Distribution .. 122. June 2005 6 Product Version Cadence Verilog -AMS Language Reference Exponential Distribution .. 123. Poisson Distribution .. 123. Chi-Square Distribution .. 124. Student's T Distribution .. 125. Erlang Distribution .. 126. Determining Whether a Parameter Value is Overridden .. 126. Interpolating with Table Models .. 127. Table Model File Format .. 128. Example .. 130. Analog Operators .. 130. Restrictions on Using Analog Operators .. 131. Limited Exponential Function .. 131. Time Derivative Operator .. 131. Time Integral Operator .. 132. Circular Integrator Operator .. 133. Delay Operator .. 135. Transition Filter.

9 136. Slew Filter .. 140. Implementing Laplace Transform S-Domain Filters .. 141. Implementing Z-Transform Filters .. 147. Displaying Results .. 151. $strobe .. 151. $display .. 154. $write .. 155. $monitor .. 155. Specifying Power Consumption .. 155. Working with Files .. 156. Opening a File .. 156. Reading from a File .. 159. Writing to a File .. 160. Closing a File .. 161. Exiting to the Operating System .. 162. Entering Interactive Tcl Mode .. 162. User-Defined Functions .. 163. Declaring an Analog User-Defined Function .. 163. Calling a User-Defined Analog Function .. 165. June 2005 7 Product Version Cadence Verilog -AMS Language Reference 10. Instantiating Modules and Primitives .. 167. Instantiating Verilog -A Modules .. 168. Creating and Naming Instances .. 168. Creating Arrays of Instances .. 169. Mapping Instance Ports to Module Ports .. 170. Connecting the Ports of Module Instances.

10 171. Port Connection Rules .. 173. Overriding Parameter Values in Instances .. 173. Overriding Parameter Values from the Instantiation Statement .. 173. Overriding Parameter Values Using defparam .. 175. Precedence Rules for Overriding Parameter Values .. 176. Instantiating Analog Primitives .. 176. Instantiating Analog Primitives that Use Array Valued Parameters .. 176. Instantiating Modules that Use Unsupported Parameter Types .. 177. Using an m-factor (Multiplicity Factor) .. 177. Passing an m-factor Down the Hierarchy .. 178. Accessing an Inherited m-factor .. 178. Example: Using an m-factor .. 178. Including Verilog -A Modules in Spectre Subcircuits .. 179. 11. Mixed-Signal Aspects of Verilog -AMS .. 181. Fundamental Mixed-Signal Concepts .. 181. Domains .. 181. Contexts .. 181. Nets, Nodes, Ports, and Signals .. 182. Mixed-signal and Net Disciplines .. 182. Behavioral Interaction.