Virtuoso AMS Environment User Guide

1 Virtuoso AMS Environment User GuideProduct Version 2004 2000-2004 Cadence Design Systems, Inc. All rights in the United States of Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USAT rademarks:Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained inthis document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence strademarks, contact the corporate legal department at the address shown above or call other trademarks are the property of their respective Print Permission:This publication is protected by copyright and any unauthorized use of thispublication may violate copyright, trademark, and other laws. Except as specified in this permissionstatement, this publication may not be copied, reproduced, modified, published, uploaded, posted,transmitted, or distributed in any way, without prior written permission from Cadence.

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3 Except as may beexplicitly set forth in such agreement, Cadence does not make, and expressly disclaims, anyrepresentations or warranties as to the completeness, accuracy or usefulness of the information containedin this document. Cadence does not warrant that use of such information will not infringe any third partyrights, nor does Cadence assume any liability for damages or costs of any kind that may result from use ofsuch Rights:Use, duplication, or disclosure by the Government is subject to restrictions as set forthin and et seq. or its AMS Environment User GuideApril 20043 Product Version .. 17 Related Documents .. 18 Typographic and Syntax Conventions .. 191 Overview of the Virtuoso AMS Designer Flow .. 21 The AMS Designer Flow Supports Both Analog and Digital Designers .. 22 Creating HDL Modules for CDBA Cellviews .. 23 Creating HDL Data as You Save CDBA Cellviews.

4 23 Creating HDL Data from Pre-existing CDBA Cellviews .. 232 Quick-Start Tutorial .. 25 The Circuit .. 25 AMS Designer Tools .. 26 Setting Up the Tutorial .. 27 Running from a Script .. 27 Running within the AMS Environment .. 28 Opening the Command Interpreter Window .. 29 Opening the Schematic and Design Configuration .. 29 Netlisting and Compiling .. 33 Elaborating and Simulating the Design .. 43 Summary .. 553 Setting Up the AMS Environment .. 57 Overview .. 58 The File .. 58 The Files .. 59 AMS Designer Supports Design Management .. 60 ContentsVirtuoso AMS Environment User GuideApril 20044 Product Version the Text Editor to Use .. 60 Specifying Fonts for the Cadence Hierarchy Editor .. 60 Preparing to Use AMS Designer from the Hierarchy Editor .. 624 Netlisting.. 67 Netlisting Modes Supported by the AMS Netlister.

5 68 Automatic Netlisting of a Cellview .. 68 Netlist Updating and Netlisting of Entire Designs .. 70 Netlisting from the UNIX Command Line .. 70 Library Netlisting .. 72 Netlisting of Cells in Response to Changes in CDF .. 74 Preparing Existing Analog Primitive Libraries for Netlisting .. 74 Specifying the Behavior of the Netlister and Compilers .. 74 Opening the AMS Options Windows .. 75 Setting Netlister Options from the Hierarchy Editor .. 77 Opening the CIW AMS Options Window .. 86 Setting Compiler Options .. 98 Viewing the AMS Netlister Log .. 126 Understanding the Output from the AMS Netlister .. 126 How Inherited Connections Are Netlisted .. 127 Inherited Signal Connections .. 128 Inherited Terminal Connections .. 129 Instance Values for Inherited Connections .. 129 Third-Party Tools and Other Cadence Tools.

6 130 How Aliased Signals Are Netlisted .. 131 How m-factors (Multiplicity Factors) Are Netlisted .. 132 How Iterated Instances Are Netlisted .. 133 Passing Model Names as Parameters .. 134 Effect of the modelname, model, and modelName Parameters .. 134 Handling of the model* and componentName Parameters .. 136 Precedence of the model* and componentName Parameters .. 136 Specifying Parameters to be Excluded from Netlisting .. 137 Ignoring Parameters for Entire Libraries .. 137 Example: Specifying Parameters to Ignore .. 140 Virtuoso AMS Environment User GuideApril 20045 Product Version to Netlist User-Defined Functions .. 140 Ensuring that Floating Point Parameters Netlist Correctly .. 143 Defining the Parameter and Specifying a Default Value .. 143 Overriding the Default Parameter for Specific Instances .. 1455 Working with Schematic Designs.

7 149 Setting Schematic Rules Checker Options for AMS Designer .. 150 Creating Cellviews Using the AMS Environment .. 152 Preparing a Library .. 152 Creating the Symbol View .. 155 Using Blocks .. 155 Creating a Verilog-AMS or VHDL-AMS Cellview from a Symbol or Block .. 157 Descend Edit .. 160 Creating a Verilog-AMS Cellview .. 161 Creating a VHDL-AMS Cellview .. 163 Creating a Symbol Cellview from a Verilog-AMS Cellview .. 165 Inherited Connections .. 167 Global Signals in the Schematic Editor .. 167 Inherited Connections in a Hierarchy .. 168 Defining Inherited Connections .. 170 How Net Expressions Evaluate .. 171 Net and Pin Properties .. 172groundSensitivity and supplySensitivity Properties .. 173 Making Connect Modules Sensitive to Inherited Connection Values .. 1766 Using External Text Designs.

8 179 Overview of Steps for Using External Text Designs .. 180 Bringing Modules into a Cadence Library .. 180 Specifying the Working Library .. 180 Compiling into Libraries .. 181 Compiling into Temporary Libraries .. 182 Listing Compiled Modules .. 183 Using Text Blocks in Schematics .. 184 Virtuoso AMS Environment User GuideApril 20046 Product Version Modules Located in a Cadence Library .. 186 Creating a Configuration .. 186 Preparing for Simulation .. 1867 Using Existing Designs in the AMS Environment .. 187 Using Analog Primitives .. 188 Using SPICE and Spectre Netlists and Subcircuits .. 188 Preparing to Use SPICE and Spectre Netlists and Subcircuits .. 188 Placing SPICE and Spectre Netlists and Subcircuits in a Schematic .. 1898 Using Test Fixtures .. 193 Creating and Using a Textual Test Fixture.

9 194 Creating a Textual Test Fixture .. 194 Using a Test Fixture .. 195 Example: Creating and Using a Test Fixture .. 1959 Using Design Configurations.. 199 Overview of Configurations .. 200 Creating a Config Cellview .. 200 Using VHDL Modules in a Configuration .. 206 Ensuring HDL Design Unit Information Is Current .. 206 Using a Configuration .. 20610 Preparing a Design for Simulation.. 209 Overview of AMS Design Prep .. 210 What AMS Design Prep Does to Prepare a Design for Simulation .. 210 When to Use AMS Design Prep .. 211 Specifying the Behavior of AMS Design Prep .. 211 Setting Options for Global Design Data .. 211 Virtuoso AMS Environment User GuideApril 20047 Product Version Global Signals .. 213 Specifying Design Variables .. 216 Specifying Model Files to Use During Elaboration .. 219 Running AMS Design Prep.

10 221 How AMS Design Prep Handles Global Signals and Design Variables .. 225 The cds_globals Module .. 226 Global Signals .. 228 Design Variables .. 22911 Elaborating, Simulating, and Plotting Results.. 231 Specifying the Behavior of the Elaborator, Simulator, and Waveform Viewer .. 232 Setting Elaborator Options .. 232 Setting Simulator Options .. 247 Setting Waveform Selection Options .. 274 Creating Probes .. 277 Defining Databases for Waveforms .. 281 Selecting Instances from the Virtuoso Schematic Editing Window .. 282 Selecting Buses .. 283 Selecting Instances from the Scope Navigator .. 284 Copying and Pasting Within Tables .. 285 Elaborating and Simulating .. 286 Viewing Messages .. 289 Plotting Waveforms After Simulation Ends .. 290 Starting the SimVision Waveform Viewer .. 291 Plotting Waveforms Selected on a Schematic (Direct Plot).