Transcription of Chapter 7, Combinational Circuit Design: VHDL Description ...
1 ECE 545 Required reading Lecture 7 P. Chu, RTL Hardware design using vhdl . Chapter 7, Combinational Circuit design : vhdl Description of Basic Practice Combinational & sequential Chapter , vhdl Process Chapter 8, sequential Circuit design : Circuit Building Blocks Principle (except subchapter ). Slides for Chapter 8, available at George Mason University 2. Fixed Logical Shift Right in vhdl . SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);. SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);. 4. A(3) A(2) A(1) A(0). Fixed Shifters & Rotators A. A. >>1. C L. 4 C. 0' A(3) A(2) A(1). ECE 448 FPGA and ASIC design with vhdl 3 4. Fixed Logical Shift Right in vhdl Fixed Arithmetic Shift Right in vhdl . SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);. SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0).
2 4. A(3) A(2) A(1) A(0) 4. A(3) A(2) A(1) A(0). A A. A A. >>1 >>1. C L C A. 4 C 4 C. 0' A(3) A(2) A(1) A(3) A(3) A(2) A(1). C <= '0' & A(3 downto 1);. 5 6. 1. Fixed Arithmetic Shift Right in vhdl Fixed Logical Shift Left in vhdl . SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);. SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);. 4. A(3) A(2) A(1) A(0) 4. A(3) A(2) A(1) A(0). A A. A A. >>1 <<1. C A C L. 4 C 4 C. A(3) A(3) A(2) A(1) A(2) A(1) A(0) 0'. C <= A(3) & A(3 downto 1);. 7 8. Fixed Logical Shift Left in vhdl Fixed Rotation Left in vhdl . SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);. SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);. 4. A(3) A(2) A(1) A(0) 4.
3 A(3) A(2) A(1) A(0). A A. A A. <<1 <<< 1. C L C. 4 C 4 C. A(2) A(1) A(0) 0' A(2) A(1) A(0) A(3). C <= A(2 downto 0) . 9 10. Fixed Rotation Left in vhdl . SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);. SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);. 4. A(3) A(2) A(1) A(0). A Variable Rotators A. <<< 1. C. 4 C. A(2) A(1) A(0) A(3). C <= A(2 downto 0) . 11 ECE 448 FPGA and ASIC design with vhdl 12. 2. 8-bit Variable Rotator Left 8. A. 3 Multiplexers B A <<< B. C. 8. To be covered during the next class 13 ECE 448 FPGA and ASIC design with vhdl 14. 2-to-1 Multiplexer 2-to-1 Multiplexer s s s f s f w w 0 0 w 0 0 w f 0 0 f 0 0. w w 1 1 1 w 1 1 1 w 1 1. (a) Graphical symbol (b) Truth table (a) Graphical symbol (b) Truth table vhdl : vhdl : f <= w0 WHEN s = '0' ELSE w1 ;. or f <= w1 WHEN s = '1' ELSE w0 ;. 15 16.
4 Cascade of two multiplexers Cascade of two multiplexers w 0 w 0. 3 3. 0 0. w 1 y w 1 y 2 w 2 w 1 1 1 1. s2 s2. s1 s1. vhdl : vhdl : f <= w1 WHEN s1 = '1' ELSE. w2 WHEN s2 = '1' ELSE. w3 ;. 17 18. 3. 4-to-1 Multiplexer 4-to-1 Multiplexer (a) Graphic symbol (b) Truth table (a) Graphic symbol (b) Truth table s s s 0. s s f s 0. s s f s 1 0 s 1 0. 1 1. w 0 0 w w 0 0 w 0 00 0 0 00 0. w 0 1 w w 0 1 w 1 01 1 1 01 1. f f w 1 0 w w 1 0 w 2 10 2 2 10 2. w 11 1 1 w w 11 1 1 w 3 3 3 3. WITH s SELECT. f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ;. 19 20. 2-to-4 Decoder (b) Graphical symbol (a) Truth table w y w 1 3. w y En w w y y y y 0 2. 1 0 3 2 1 0 y y 1. Decoders 1 0 0. En y 0. 1 0 1. 1 1 0. 1 1 1. 0 x x ECE 448 FPGA and ASIC design with vhdl 21 22. 2-to-4 Decoder 2-to-4 Decoder (b) Graphical (b) Graphical symbol symbol (a) Truth table w y (a) Truth table w y w 1 3 w 1 3.
5 W y w y En w w y y y y 0 2 En w w y y y y 0 2. 1 0 3 2 1 0 y 1 0 3 2 1 0 y y y 1 1. 1 0 0 0 0 0 1 y 1 0 0 0 0 0 1 y En 0 En 0. 1 0 1 0 0 1 0 1 0 1 0 0 1 0. 1 1 0 0 1 0 0 1 1 0 0 1 0 0 Enw <= En . 1 1 1 1 0 0 0 1 1 1 1 0 0 0 WITH Enw SELECT. y <= "0001" WHEN "100", 0 x x 0 0 0 0 0 x x 0 0 0 0 "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", "0000" WHEN OTHERS ;. 23 24. 4. vhdl code for a 2-to-4 Decoder entity LIBRARY ieee ;. USE ;. ENTITY dec2to4 IS. PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;. En : IN STD_LOGIC ;. y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;. END dec2to4 ;. ARCHITECTURE dataflow OF dec2to4 IS. Encoders SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;. BEGIN. Enw <= En . WITH Enw SELECT. y <= "0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", "0000" WHEN OTHERS.
6 END dataflow ;. 25 ECE 448 FPGA and ASIC design with vhdl 26. Priority Encoder Priority Encoder w0 w0. y0 y0. w1 y w1 y w w2. y1 w w2. y1. w3 z w3 z w3 w2 w1 w0 y1 y0 z w3 w2 w1 w0 y1 y0 z 0 0 0 0 0 0 0 0 d d 0. 0 0 0 1 0 0 0 1 0 0 1. 0 0 1 - 0 0 1 - 0 1 1. 0 1 - - 0 1 - - 1 0 1. 1 - - - 1 - - - 1 1 1. 27 28. Priority Encoder vhdl code for a Priority Encoder entity LIBRARY ieee ;. USE ;. w0. y0. w1 y ENTITY priority IS. w w2. y1 PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;. y <= "11" WHEN w(3) = '1' ELSE y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;. w3 z "10" WHEN w(2) = '1' ELSE z : OUT STD_LOGIC ) ;. "01" WHEN w(1) = '1' ELSE END priority ;. "00" ;. w3 w2 w1 w0 y1 y0 z ARCHITECTURE dataflow OF priority IS. z <= '0' WHEN w = "0000" ELSE '1' ; BEGIN. 0 0 0 0 d d 0 y <= "11" WHEN w(3) = '1' ELSE.
7 0 0 0 1 0 0 1 "10" WHEN w(2) = '1' ELSE. 0 0 1 - 0 1 1 "01" WHEN w(1) = '1' ELSE. 0 1 - - 1 0 1 "00" ;. 1 - - - 1 1 1 z <= '0' WHEN w = "0000" ELSE '1' ;. END dataflow ;. 29 30. 5. Adder mod 216. 16 16. X Y. Adders S. 16. ECE 448 FPGA and ASIC design with vhdl 31 32. vhdl code for an Adder mod 216 Signed and Unsigned Types LIBRARY ieee ;. USE ;. USE ; Behave exactly like ENTITY adder16 IS STD_LOGIC_VECTOR. PORT ( X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;. Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; plus, they determine whether a given vector S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;. END adder16 ; should be treated as a signed or unsigned number. ARCHITECTURE dataflow OF adder16 IS Require BEGIN. S <= std_logic_vector(unsigned(X) + unsigned(Y));. USE ;. END dataflow ;. 33 34. 16-bit Unsigned Adder Addition of Unsigned Numbers (1).
8 LIBRARY ieee ;. USE ;. 16 16 USE ;. X Y ENTITY adder16 IS. Cout + Cin PORT ( Cin X. : IN. : IN. STD_LOGIC ;. STD_LOGIC_VECTOR(15 DOWNTO 0) ;. S Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;. S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;. 16 Cout : OUT STD_LOGIC ) ;. END adder16 ;. 35 36. 6. Addition of Unsigned Numbers (3). ARCHITECTURE dataflow OF adder16 IS. signal Sum: unsigned(16 DOWNTO 0) ;. BEGIN. Sum <= unsigned('0' & X) + unsigned(Y) + unsigned('0' . S <= std_logic_vector(Sum(15 downto 0));. Cout <= Sum(16) ; Multipliers END dataflow ;. 37 ECE 448 FPGA and ASIC design with vhdl 38. Unsigned vs. Signed Multiplication 8x8-bit Unsigned Multiplier Unsigned Signed 8 8. a b 1111 15 1111 -1. x 1111 x 15 x 1111 x -1. *. c U. 16. 11100001 225 00000001 1. 39 40. 8x8-bit Signed Multiplier 8x8-bit Unsigned and Signed Multiplier 8 8 8 8.)
9 A b a b *. c S cu cs 16 16 16. 41 42. 7. Multiplication of signed and unsigned numbers LIBRARY ieee;. USE ;. USE ;. entity multiply is port(. a : in STD_LOGIC_VECTOR(7 downto 0);. b : in STD_LOGIC_VECTOR(7 downto 0);. cu : out STD_LOGIC_VECTOR(15 downto 0);. );. cs : out STD_LOGIC_VECTOR(15 downto 0) ROM. end multiply;. architecture dataflow of multiply is begin -- signed multiplication cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b));. -- unsigned multiplication cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b) );. end dataflow;. 43 ECE 448 FPGA and ASIC design with vhdl 44. ROM 8x16 example (1) ROM 8x16 example (2). LIBRARY ieee;. USE ;. USE ;. 3. ENTITY rom IS. Addr PORT (. Addr : IN STD_LOGIC_VECTOR(2 DOWNTO 0);. 8x16 Dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0). ROM );. END rom;. Dout 16. C. 45 46.
10 ROM 8x16 example (3) ROM 8x16 example (4). ARCHITECTURE dataflow OF rom IS ARCHITECTURE dataflow OF rom IS. SIGNAL temp: INTEGER RANGE 0 TO 7; TYPE vector_array IS ARRAY (0 to 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0);. TYPE vector_array IS ARRAY (0 to 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0); CONSTANT memory : vector_array :=. CONSTANT memory : vector_array := ( X"800A", ( X"800A", X"D459", X"D459", X"A870", X"A870", X"7853", X"7853", X"650D", X"650D", X"642F", X"642F", X"F742", X"F742", X"F548");. X"F548"); BEGIN. BEGIN. Dout <= memory(to_integer(unsigned(Addr)));. temp <= to_integer(unsigned(Addr));. Dout <= memory(temp); END dataflow;. END dataflow;. 47 48. 8. Tri-state Buffer e x f e=0. (a) A tri-state buffer x f Buffers e x f e=1. x f 0 0. 0 1. 1 0 (b) Equivalent Circuit 1 1. (c) Truth table ECE 448 FPGA and ASIC design with vhdl 49 50.
