Example: tourism industry
Computer Architecture: Multithreading
128 x 32 general purpose registers 128 x 1 thread status registers 14 Coarse-grained Multithreading Idea: When a thread is stalled due to some event, switch to a different hardware context Switch-on-event multithreading Possible stall events Cache misses Synchronization events (e.g., load an empty location) FP operations
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Computer Architecture: Dataflow (Part I)
course.ece.cmu.eduComputer Architecture,” ACM Computing Surveys 1982. ! Veen, “Dataflow Machine Architecture,” ACM Computing Surveys 1986. ! Gurd et al., “The Manchester prototype dataflow computer,” CACM 1985. ! Arvind and Nikhil, “Executing a Program on the MIT Tagged-Token Dataflow Architecture,” IEEE TC 1990. !
Computer Architecture: Vector Processing: SIMD/Vector/GPU ...
course.ece.cmu.eduCarnegie Mellon University Vector Processing: Exploiting Regular (Data) Parallelism Data Parallelism Concurrency arises from performing the same operations on different pieces of data Single instruction multiple data (SIMD) E.g., dot product of two vectors Contrast with data flow
Computer Architecture: Branch Prediction
course.ece.cmu.eduHow to Handle Control Dependences Critical to keep the pipeline full with correct sequence of dynamic instructions. Potential solutions if the instruction is a control-flow instruction: Stall the pipeline until we know the next fetch address Guess the next fetch address (branch prediction) Employ delayed branching (branch delay slot) Do something else (fine-grained multithreading)
Computer Architecture: Main Memory (Part I)
course.ece.cmu.eduMemory Bank Organization and Operation Read access sequence: 1. Decode row address & drive word-lines 2. Selected bits drive bit-lines • Entire row read 3. Amplify row data 4. Decode column address & select subset of row • Send to output 5. …
CMOS Power Consumption - ECE:Course Page
course.ece.cmu.eduWays to reducing power consumption Load capacitance (C L) ⌧Roughly proportional to the chip area Switching activity (avg. number of transitions/cycle) ⌧Very data dependent ⌧A big portion due to glitches (real-delay) Clock frequency (f) ⌧Lowering only f decreases average power, but total energy is the same and throughput is worse 1.00 1 ...
MOSFET transistor I-V characteristics
course.ece.cmu.eduDepletion Mode NMOSFET • Depletion mode FETs have a channel implanted such that there is conduction with V GS=0 • The operation is the same as the enhancement mode FET, but the threshold voltage is shifted •Vt is negative for depletion NMOS, and positive for depletion PMOS VGS n+ n+ VS VDS n+ p
HDL Compiler for Verilog Reference Manual
course.ece.cmu.eduComments? E-mail your comments about Synopsys documentation to doc@synopsys.com HDL Compiler for Verilog Reference Manual Version 2000.05, May 2000
A Primer on Memory Consistency and Cache Coherence
course.ece.cmu.eduDaniel J. Sorin, Duke University Mark D. Hill and David A. Wood, University of Wisconsin, Madison ... We thank Blake Hechtman for implementing and testing (and debugging!) all of the coherence protocols in this primer. As the reader will soon …
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