Computer Bus Structures - California State …

1 1 Computer Bus StructuresComputer Bus StructuresRamin Roosta2 IntroductionIntroductionzConcept of the basic buszDescription of available Internal bus SystemszDescription of available External bus systems3 Basic BusBasic BuszData buszAddress buszHandshaking lineszControl lines4 Data BusData BuszFunction of a data bus is to send data from one device to anotherzData is passed in parallel or serial manner Parallel will normally pass in a multiple of 8-bits at a time Serial passes one bit at a time5zParallel data bus is fasterzParallel data bus requires an extra handshaking line to synchronize the data transfer6 Address BusAddress CPU needs to read an instruction (data) from a given location in memoryzIdentify the source or destination of datazBus width determines maximum memory capacity of system 8080 has 16 bit address bus giving 64k address spaceAddress Bus Size Addressable memory (bytes)122438416532664712882569512101K11 2K124K138K1416 KAddressable memory in bytes/address bus size7 Data Handshaking LinesData Handshaking LineszCritical for the flow of orderly datazBasic Handshaking consists of two lines.

2 -Sending identification line-Receiving identification line8 Control LinesControl Lines Memory write Memory read I/O write I/O read Transfer ACK Bus request Bus grant Interrupt request Interrupt ACK Clock ResetzControls the access to the data and address lineszControls the use of the data and address lineszTypical control lines include the following:9 BUS Interconnection SchemeBUS Interconnection Scheme10 Bus TypeBus TypezDedicated Separate data & address lineszMultiplexed Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages More complex control Ultimate performance11 Bus ArbitrationBus ArbitrationzMore than one module controlling the CPU and DMA controllerzOnly one module may control bus at one timezArbitration may be centralised or distributed12 Method of ArbitrationMethod of ArbitrationCentralizedzSingle hardware device controlling bus access Bus Controller ArbiterzMay be part of CPU or separateDistributedzEach module may claim the buszControl logic on all modules13 TimingTimingzCo-ordination of

3 Events on buszSynchronous Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle All devices can read clock line Usually sync on leading edge Usually a single cycle for an eventzAsynchronous Occurrence of one event on a bus depends on previous events14 Synchronous Timing DiagramSynchronous Timing Diagram15 Asynchronous TimingAsynchronous TimingWrite cycleRead cycle16 Bus WidthBus WidthzWider data bus = Greater number of bits at one timezWider address bus = Greater range of locations that can be referenced17 Busses CoveredBusses CoveredParallelSerialParallelSerialS-100 I2 CATAACCESS BUSISASPIIEEE-488 ADBEISAH iper Transport HIPPIF ibre ChannelMCAPCI-EXPRESS PCMCIAIEEE-1394 NUBUSSCSIRS-422 & RS-485 SBUSS erial ATAPCISSAVMEUSBVESACANINTERNAL BUSSESEXTERNAL BUSSES18 PCIPCIzPeripheral Component InterconnectionzAn example of an internal parallel buszHigh bandwidthzIntel released to public domainz32 or 64 bitz50 lines @ 66 MHzzTransfer Rate of 528MB/s19 System of TodaySystem of TodayProcessorCacheBridge/MemoryControll erDRAMA udioMotionVideoLANPCI toISAS uper I/OGraphicsFAX/ModemKeyboardMouseRTCBIOS ISA toPCMCIAIDEPCI BusISA BusPCMCIA Bus20 PCI Bus Lines RequiredPCI Bus Lines RequiredzSystems lines Including clock and resetzAddress & Data 32 time mux lines for address/data Interrupt & validate lineszInterface ControlzArbitration Not shared Direct connection

4 To PCI bus arbiterzError lines21 Optional PCI Bus LinesOptional PCI Bus LineszInterrupt lines Not sharedzCache supportz64-bit Bus Extension Additional 32 lines Time multiplexed 2 lines to enable devices to agree to use 64-bit transferzJTAG/Boundary Scan For testing procedures22 PCI CommandsPCI CommandszTransaction between initiator (master) and targetzMaster claims buszDetermine type of transaction I/O read/writezAddress phasezOne or more data phases23 PCI Read Timing DiagramsPCI Read Timing Diagrams24 Bus ArbitrationBus Arbitration25 SCSISCSIzSmall Computer System high-speed, intelligent peripheral I/O bus with a device independent protocol. It allows different peripheral devices and hosts to be interconnected on the same bus.

5 Depending on the type of SCSI, you may have up to 8 or 16 devices connected to the SCSI must be at least one initiator (usually a host) and one target (a peripheral device) on a is a large variety of peripheral devices available for SCSI, including hard disk drives, floppy drives, CDs, optical storage devices, tape drives, printers and scanners to name a Bus PhasesSCSI Bus PhaseszBUS Free Phase BUS FREE phase begins when the SEL and BSY signals are both continuously false for a bus settle delay. It ends when the BSY signal becomes true. zArbitration Phase In this State a unit can take control of the bus and become an Bus Phases (cont d)SCSI Bus Phases (cont d)zSelection Phase In this State the initiator selects a target unit and gets the target to carry out a given function, such as reading or writing Bus Phases (cont d)SCSI Bus Phases (cont d)zMessage Phase This is the first information transfer phase in the connection.

6 It allows the initiator to send an Identify message to the target. Messages are always transferred asynchronously 30 SCSI Bus Phases (cont d)SCSI Bus Phases (cont d)zCommand Phase The command phase is used by the target to request command information from the In Phase The target responds with Inquiry data. The data is transferred synchronously if both the target and the initiator have previously established a synchronous data transfer agreement 31 SCSI Bus (cont d)SCSI Bus (cont d)zStatus Phase The target sends a single status byte asynchronously zMessage In Phase The last information that is transferred in the connection is typically the Command Complete message zBack to Bus Free Phase32 Varieties of SCSIV arieties of SCSIzSCSI-1 zSCSI-2 zWide SCSI zFast SCSI zFast Wide SCSI zUltra SCSI zSCSI-3 zUltra2 SCSI zWide Ultra2 SCSI33 SCSI vs.

7 ATA (IDE, EIDE)SCSI vs. ATA (IDE, EIDE)zSCSI does not utilize the CPU for data transfer is more expensive than EIDEzSCSI can handle more devices34 FibreFibreChannelChannelzFibre Channel is an open T11 and ANSI standards-based block-oriented serial network protocol that brings together some of the best features of the channel world and the network Channel is full-duplex (Full duplex means that data can travel in both directions simultaneously.), and offers a variety of different cabling it is cost effective for storage and networkszReliable it is reliable with assured information deliveryzGigabit bit rate Gbps, scalable to Gbps and GbpszMultiple topologies it has dedicated point-to-point, shared loops, and scaled switched topologies meet application requirements36 Advantages (cont d)Advantages (cont d)zMultiple protocols it supports SCSI, TCP/IP, video, or raw data , and is especially suited to real-time it supports single point-to-point gigabit links to integrated enterprises with hundreds of Free data can be sent as fast as the destination buffer can receive (cont d)Advantages (cont d)

8 ZHigh Efficiency fibre channel has very little transmission overhea