Cool-Power ZVS Switching Regulators

1 Cool-Power ZVS Switching Regulators Rev 1 of 49 08/20178V 60 VIN , 10V 50 VOUT , 50 140W Cool-Power ZVS Buck-Boost RegulatorCool- power ZVS Switching RegulatorsPI3740-00 Product DescriptionThe PI3740-00 is a high efficiency, wide input and output range DC-DC ZVS Buck-Boost Regulator. This high density System-in-Package (SiP) integrates controller, power switches, and support components. The integration of a high performance Zero-Voltage Switching (ZVS) topology within the PI3740-00 increases point of load performance, providing best in class power PI3740-00 requires an external inductor, resistive divider and minimal capacitors to form a complete DC DC Switching mode buck-boost ZVS architecture also enables high frequency operation while minimizing Switching losses and maximizing efficiency.

2 The high Switching frequency operation reduces the size of the external filtering components, improves power density, and enables fast dynamic response to line and load & Benefits Up to 96% efficiency 50 140W continuous output power Parallel capable with single wire current sharing External frequency synchronization / interleaving High Side Current Sense Amplifier General Purpose Amplifier Lighting / Constant Current Mode (LGH) Input Over / Undervoltage Lockout (OVLO / UVLO) Output Overvoltage Protection (OVP) Overtemperature Protection (OTP) Fast and slow current limits -40 C to 115 C operating range (TJ) Excellent light load efficiencyApplications Battery Charging and Conditioning, Telecom, Networking, Lighting Computing, Communications, Industrial, Automotive Accessories 12V, 24V.

3 48V and 60V DC DC ApplicationsPackage Information 10mm x 14mm x LGA SiPPI3740-0010kCINVINPGNDVS1VS2 VOUTISPPGNDISNIMONVSNVSPCOMPEAOEAINVDIFF LGHCOUTR1R2 CHFCCOMPSYNC ITRKSGNDENSYNC OPGDVDRCTRKT ypical ApplicationDeviceOutput VoltageSetRangePI3740-00-LGIZ12V10 to 50 VCool- power ZVS Switching Regulators Rev 2 of 49 08/2017PI3740-00 ContentsOrder Information 3 Absolute maximum Ratings 3 Pin Description 4 Package Pin-Out 5 Large Pin Blocks 5 Storage and Handling Information 6 Block Diagram 6PI3740-00-LGIZ Electrical Characteristics 7PI3740-00-LGIZ Performance Characteristics 11 MTBF 19 Functional Description 20 Enable 20 Switching Frequency Synchronization 20 Soft-Start and Tracking 20 Remote Sensing Differential Amplifier 20 power Good 20 Output Current Limit Protection 20 Input Undervoltage Lockout 20 Input Overvoltage Lockout 20 Output Overvoltage Protection 21 Overtemperature Protection 21 Pulse Skip Mode (PSM)

4 21 Variable Frequency Operation 21 IMON Amplifier 21 Application Description 22 Output Voltage Trim 22 Soft-Start Adjustment and Tracking 22 Inductor Pairing 22 Filter Considerations 23PI3740-00 maximum COUT Capability at Startup 26 Thermal Design 27 Thermal Design Inductor 29PI3740-00-LGIZ Percentage of SiP Loss to Total Loss 31 Evaluation Board Thermal De-rating 33 Parallel Operation 35 Synchronization 35 Interleaving 35 Small Signal Models CV-CC Modes 36 Small Signal Model Constant Voltage Mode 36 Error Amplifier 36 Lighting Mode (LGH) 36 LGH Amplifier Small Signal Model 37 VDR Bias Regulator 37PI3740-00-LGIZ Modulator Gain / Output Resistance 38 System Design Considerations 45 Package Drawings 46 Receiving PCB Pattern Design Recommendations 47 Revision History 48 Product Warranty 49 Cool-Power ZVS Switching Regulators Rev 3 of 49 08/2017PI3740-00 Order InformationAbsolute maximum RatingsNote: Stresses beyond these limits may cause permanent damage to the device.

5 Operation at these conditions or conditions beyond those listed in the Electrical Specifications table is not guaranteed. All voltage nodes are referenced to PGND unless otherwise noted.[1] Transient VS1 voltages are guaranteed by design when the specified 420nH 10% inductor is used.[2] Non-Operating Test Mode Limits.[3] The ISP pin to ISN pin has a maximum differential limit of + and NumberDescriptionPackageTransport MediaMFGPI3740-00-LGIZVIN 8 60V, VOUT 10 50V10mm x 14mm 108-pin LGATRAYV icorLocationNameVMAXVMINISOURCEISINK1 2, G [2]40A [2]4 5, G [1]40A [2]18A [2]10 11, G [1]40A [2]18A [2]13 14, G [2]40A [2] [3]75V-2 VDC5mA5mA14 EISP [3]75V-2 VDC5mA5mA10 14, B + 10 12, C 9, B E + 7 8, F KPGNDN/AN/A18A [2]18A [2] Cool-Power ZVS Switching Regulators Rev 4 of 49 08/2017PI3740-00 Pin DescriptionPin NumberPin NameDescription1 2, G KVINI nput voltage and sense node for UVLO, OVLO and feed forward 5, G KVS1 Input side Switching node and ZVS sense node for power 11, G KVS2 Output side Switching node and ZVS sense node for power 14, G KVOUTO utput voltage and sense node for power switches, VOUT feed forward compensation, VOUT_OV and internal supply for gate drivers and internal logic.

6 May be used as reference or low power bias supply for up to 2mA. Must be impedance limited by the & power Good indicator. PGD pulls low when the regulator is not operating or if EAIN is less than output. Outputs a high signal for of the programmed Switching period at the beginning of each Switching cycle, for synchronization of other Regulators . 1 BSYNCIS ynchronization input. When a falling edge synchronization pulse is detected, the PI3740-00 will delay the start of the next Switching cycle until the next falling edge sync pulse arrives, up to a maximum delay of two times the programmed Switching period. If the next pulse does not arrive within two times the programmed Switching period, the controller will leave sync mode and start a Switching cycle automatically. Connect to SGND when not in use.

7 1 AFT1 For factory use only. Connect to SGND or leave floating in factory use only. Connect to SGND or leave floating in factory use only. Connect to SGND in factory use only. Connect to SGND in Enable control. Asserted high or left floating regulator enabled;Asserted low, regulator output disabled. 6 ATRKSoft-start and track input. An external capacitor must be connected between TRK pin and SGND to decrease the rate of output rise during soft-start. Recommended value is 47nF for for constant current lighting amplifier. Connect to SGND if not in amp compensation dominant pole. Connect a capacitor of 4700pF by default between COMP and SGND to set the control loop dominant pole. 9 AVSNG eneral purpose amplifier inverting purpose amplifier non-inverting Purpose amplifier output.

8 When unused connect VDIFF to VSN and VSP to amplifier inverting input and sense for PGD. Connect by resistive divider to the amp output: External connection for additional compensation and current sharing. Add 56pF capacitor from EAO to side current sense amplifier side current sense amplifier negative side current sense amplifier positive 14, B + 10 12, C ESGNDS ignal ground. Internal logic and analog ground for the regulator. SGND and PGND are star connected within the regulator 9, B E + 7 -8, F KPGNDP ower ground. VIN, VOUT, VS1 and VS2 power returns. SGND and PGND are star connected within the regulator ZVS Switching Regulators Rev 5 of 49 08/2017PI3740-001234567891011121314 SGNDSGNDSGNDSGNDSGNDSGNDSGNDSGNDSGNDSGND SGNDSGNDSGNDSGNDPGNDPGNDPGNDPGNDPGNDPGND PGNDPGNDPGNDPGNDPGNDPGNDPGNDPGNDPGNDPGND PGNDPGNDPGNDPGNDPGNDPGNDPGNDPGNDPGNDPGND PGNDPGNDPGNDPGNDPGNDPGNDPGNDPGNDPGNDPGND PGNDPGNDPGNDPGNDPGNDPGNDIMONFT1FT2FT3FT4 ENTRKLGHCOMPVSNVSPVDIFFEAINEAOVINVDRPGDS YNC0 SYNCIVS1 VINVINVINVINVINVINVINVS1VS1VS1VS1VS1 VOUTISPISNVOUTVOUTVOUTVOUTVOUTVOUTVS2 VOUTVS2VS2VS2VS2VS2VS2VS2VS1VS1 Package Pin-OutPin Block NameGroup of pinsVING1-2, H1-2, J1-2, K1-2VS1G4-5, H4-5, J4-5, K4-5 PGNDB2-9, C2-9, D2-9, E2-9, F7-8, G7-8, H7-8, J7-8, K7-8VS2G10-11, H10-11, J10-11, K10-11 VOUTG13-14, H13-14, J13-14, K13-14 SGNDB10-14, C10-12, D10-12.

9 E10-12 Large Pin BlocksCool- power ZVS Switching Regulators Rev 6 of 49 08/2017PI3740-00 IMONISP+-ISNVINPGNDSGNDSYNC OFLTVCCFT1 ENSYNC ITRKEAOZVS Buck Boost ControlandDigital Parametric TrimPower Control+-0 +-+ DiagramStorage and Handling InformationStorage Temperature-65 C to 150 CInternal Operating Temperature-40 C to 115 CSoldering Temperature for 20 seconds245 CMSL Rating3 ESD Rating [4] HBM; CDM[4] JS-200-2014, ZVS Switching Regulators Rev 7 of 49 08/2017PI3740-00PI3740-00-LGIZ Electrical CharacteristicsSpecifications apply for the conditions -40 C < TJ < 115 C, VIN = 24V, VOUT = 12V, LEXT = 420nH [5], external CIN = 6 x F, external COUT = 8 x 10 F, unless otherwise SpecificationsInput VoltageVIN_DC82460 VInput Current During Output Short(fault condition duty cycle)IIN_SHORT[6] Quiescent CurrentIQ_VINE nabled (no load)

10 5mAInput Quiescent CurrentIQ_VIND isabled2mAInput Voltage Slew RateVIN_SR[6]1V / sInternal Input CapacitanceCIN25 C, VIN = FVIN UVLO threshold UVLO OVLO threshold OVLO SpecificationsEAIN Voltage Total Voltage RangeVOUT_DC101250 VOutput Current RangeIOUT_DCR[7]0 See note 6 AOutput Current Steady StateIOUT_DCVIN = 8 16V, VOUT 12V, TCASE = 25 C [7] = 16 24V, VOUT 12V, TCASE = 25 C [7] power Steady StatePOUT_DCVIN = 8 60V, VOUT = 12 36V, TCASE = 25 C [7]60 WVIN = 16 28V, VOUT = 24 36V, TCASE = 25 C [7]123 maximum Array SizeNPARALLEL3 ModulesOutput Current, array of 2 IOUT_DC-ARRAY2 Total array capability, see applications section for IOUT_DC AOutput Current, array of 3 IOUT_DC-ARRAY3 Total array capability, see applications section for IOUT_DCLine Regulation VOUT ( VIN)@ 25 C, 8V < VIN < Regulation VOUT ( IOUT)@ 25 C, IOUT above 5% of the typical full RippleVOUT_ACIOUT = , VIN = 24V, VOUT = 12V, TCASE = 25 C COUT_EX = 8 x 10 F, 50V, X7R, 20 MHz BW96mVp-pInternal Output CapacitanceCOUT25 C, VOUT = FVOUT Overvoltage ThresholdVOUT_OVTR ising VOUT threshold to detect open Overvoltage Supply VoltageVDRG enerated LoadingIVDRSee Application Description for details02mA[5] See Inductor Pairing section.