Device Operation & Timing Diagram - Samsung us

1 - 1 -Rev. , ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application.

2 Or any governmental procurement to which special terms or provisions may updates or additional information about Samsung products, contact your nearest Samsung brand names, trademarks and registered trademarks belong to their respective owners. 2014 Samsung Electronics Co., Ltd. All rights Operation & Timing DiagramDDR4 SDRAM SpecificationCAUTION :The 3DS contents in this document includes some items still under discussion in JEDECT herefore, those may be changed without pre-notice based on JEDEC progressIn addition, it is highly recommended that you not send specs without Samsung s permission- 2 - Device OperationDDR4 SDRAMRev.

3 HistoryRevision First Spec releaseSep. Add 3DS Functional Description,3DS SDRAM Command Description and OperationOct. 3 - Device OperationDDR4 SDRAMRev. Of ContentsDDR4 SDRAM Specification1. Functional Description .. Simplified State Diagram .. Basic RESET and Initialization Procedure .. Power-up Initialization Sequence .. VDD Slew rate at Power-up Initialization Sequence .. Reset Initialization with Stable Power .. Register Definition .. Programming the mode registers.

4 Mode Register .. 3DS Functional Description .. Simplified State Basic Functionality .. Reset Signal and Initialization Procedure .. Mode Register Definition .. 242. DDR4 SDRAM Command Description and Operation .. Command Truth CKE Truth Table .. Burst Length, Type and Order .. BL8 Burst order with CRC DLL-off Mode & DLL on/off Switching procedure .. DLL on/off switching DLL on to DLL off DLL off to DLL on DLL-off Mode .. Input Clock Frequency Change.

5 Write Leveling .. DRAM setting for write leveling & DRAM termination function in that mode .. Procedure Write Leveling Mode Exit .. Temperature controlled Refresh modes .. Normal temperature mode ( 0 C =< TCASE =< 85 C ) .. Extended temperature mode ( 0 C =< TCASE =< 95 C ).. Fine Granularity Refresh Mode .. Mode Register and Command Truth Table .. tREFI and tRFC parameters .. Changing Refresh Usage with Temperature Controlled Refresh Self Refresh entry and exit.

6 Multi Purpose Register .. DQ Training with MPR .. MR3 definition .. MPR Reads .. MPR Writes .. MPR Read Data format .. Data Mask(DM), Data Bus Inversion (DBI) and ZQ Calibration Commands .. ZQ Calibration Description .. DQ Vref Example scripts for VREFDQ Calibration Mode: .. Per DRAM Addressability .. CAL Mode (CS_n to Command Address Latency) .. CAL Mode Description .. Self Refresh Entry, Exit Timing with CAL .. Power Down Entry, Exit Timing with CAL .. CRC.

7 CRC Polynomial and logic CRC data bit mapping for x8 CRC data bit mapping for x4 71- 4 - Device OperationDDR4 SDRAMRev. CRC data bit mapping for x16 Write CRC for x4, x8 and x16 devices .. CRC Error Handling .. CRC Frame format with BC4 .. Simultaneous DM and CRC Functionality .. Simultaneous MPR Write, Per DRAM Addressability and CRC Functionality .. Command Address Parity( CA Parity ) .. CA Parity Error Log Readout .. Control Gear-down Mode .. DDR4 Key Core Timing .

8 Programmable Write Preamble .. Read Preamble .. Read Preamble Training .. Read Write Postamble .. ACTIVATE Command .. Precharge Command .. Read Operation .. READ Timing READ Timing ; Clock to Data Strobe relationship .. READ Timing ; Data Strobe to Data relationship .. tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .. tRPRE Calculation .. tRPST Calculation .. READ Burst Operation .. Burst Read Operation followed by a Burst Read Operation with Read DBI (Data Bus Inversion).

9 Burst Read Operation with Command/Address Parity .. Read to Write with Write Read to Read with CS to CA Latency .. Write Operation .. Write Timing Parameters .. Write Data tWPRE tWPST Calculation .. Write Burst Read and Write Command Interval .. Write Timing Violations .. Motivation .. Data Setup and Hold Offset Violations .. Strobe and Strobe to Clock Timing Refresh Command .. Self refresh Operation .. Low Power Auto Self Refresh .. Self Refresh Exit with No Operation command.

10 Power down Mode .. Power-Down Entry and Exit .. Power-Down clarifications .. Power Down Entry and Exit Timing during Command/Address Parity Mode is Enable .. Maximum Power Saving Mode .. Maximum power saving mode .. Mode CKE transition during the mode .. Mode Timing parameter bin of Maximum Power Saving Mode for DDR4-1600/1866/2133/2400/2666/3200 .. Connectivity Test Mode .. Introduction .. Pin Mapping .. Logic Min Term Output equations for x16 devices .. 155- 5 - Device OperationDDR4 SDRAMRev.