dvanced Packaging Technologies for Miniaturized Modules

1 dvanced Packaging Technologies for MiniaturizedModulesVinayak PandeyVP, Product Technology Marketing, STATS ChipPACForm FactorPerformanceIntegrationLow CostAnalog Package RequirementsAnalog Package TrendsfcQFN FCOL/MIS QFN-dr/mr2L WB laminate/ 1L(Single Metal SueWLB 1L RDLQFNQFP1L WB - MIS1/2L FC - MISMIS can be used for leaded/laminate wirebond& flip chip Packaging eWLB drives superior performance and integrationFlip chipWirebondSingle Metal SubstrateFlip Chip on LeadFrameMolded Interconnect Substrate/systemEmbedded Wafer Level Ball Grid ArrayMIS (Molded Interconnect System/Substrate)Carrier4 Pre-mold compoundFinish plating.)

2 NiPdAu, NiAu, Cu+OSPS urface finish(Cu+OSP / NiAu/ NiPdAu) 1 LMIS substrate 4B 250x70mm ( thickness)Cross section viewRoutableExternal leadTrace 1L MIS Process FlowORMIS Design & Application1 LMIS (PM Application)Package thickness: pitch: pitch: structure: Cu pillar bump with tin capBump height: 90um (65um copper + 25um solder)Bump size: 110umBump material: Sn/Ag sectionfcQFN-1L MIS delaminationPost MSL 1 / TCT 1500 cycles / uHAST 43D MIS PackagingCharacteristics Passive components Multi-chip module 3D MIS substrate Large area metal and partial fine line/spaceAdvantagesSuperior electrical and thermal performanceHigh reliability performanceCross section view of 3D MIS packagingFlip chip on 3D MISP assive components mounted on package top3D MIS package for wearablecommunication devicefcMISS tructure:Substrate thickness Bump Pitch.

3 90 umCu column interconnectMolded UnderfillReadout pointLeTC B 1000x w/ MSL3 SATI mageO/S testPassed (TC B 1000x w/ MSL2aaSATI mageO/S testPassed (Reliability Results:Structure:substrate thickness Bump Pitch : 80 umCu column interconnectMolded UnderfillConventional Fan-in WLP (WLCSP)Interconnect is limited to die sizeCompact package sizeHigher performanceLower cost than BGAs or laminate based CSPsSilicon dieSilicon dieFan-out WLP (eWLBI nterconnect is independent of d Small package size Dramatically higher I/O count Strong thermal & electrical perform Able to integrate die from diverse silicon nodes Cost effective advanced package Wafer Level PackagingSilicon dieeWLB provides the operformance soluincreased I/O densitFine Cu Plated RDL 5/5um LW/LS10 mUltra Th~ withIntegration with discrete and RDL inductor)))

4 Small form factor Increased performance integration Cost effective solutionSi3-L ReWLBC apabilitiesFOWLP is a versatile technology platformsemiconductor industry s evolution from designs to interposers and 3D IC inSingle chip eWLBeWLLFlip Chip eWLB3D eWLB with Interposer3D / Extended eWLBeWLB-PoP ( )Multi-chipFOWLP/eWLB EvolutionFOWLP breaks into New Frontiers!by-Side: Multi-die and SiP applicationsAnalog + Logic package level integration HVM from 2012)Functional partitioning -scale side-by-side MultichipAlternative solution of InterposerThinner ProfileSystem IntegraWide Range of SiP Inverted FOWLP, a Disruptive SolutionAssembly Summary:MEMS Individually bumped and singulatedASIC Individually singulated and reconstituted with thru-vias Followed by backgrind, redistribution and singulationPre-stack: ASIC and MEMS Modules pre-stack and reflowMEMS ASICT hank You