ECE 4750 Computer Architecture, Fall 2017 Course …

1 ECE 4750 Computer architecture , fall 2020 Course SyllabusSchool of Electrical and Computer EngineeringCornell Universityrevision: 2020-09-11-15-311. Course InformationCross ListedCS 4420 Computer ArchitecturePrereqsECE 3140 (cross listed as CS 3420) or CS 3410 InstructorProf. Christina Delimitrou, 332 Rhodes Hall, Hours: Online on Zoom, Tuesday, 3:00 4:30pmAdmin. AssistantKimberly Budd, TAsZhuangzhuangZhouzz586 Office/Lab Hours: Zoom, TBDYu Ganyg397 Office/Lab Hours: Zoom, TBDU ndergraduateRyan McMahonrm756 Office/Lab Hours: Zoom, TBDTAsTamzid Ahmedta326 Office/Lab Hours: Zoom, TBDA nthony Ngomaan474 Office/Lab Hours: Zoom, TBDS ujith Rameshsn438 Office/Lab Hours: Zoom, TBDL ecturesOnline on Zoom, Monday and Wednesday, 1:25 2:40pmDisc. SectionOnline on Zoom, Friday, 1:50 2:40pmRequiredJ.

2 L. Hennessy and D. A. PattersonMaterials Computer architecture : A Quantitative Approach 5th edition, Morgan Kaufmann, 2012 Cornell bookstore (new: $90, used: $46), Amazon ($67)On reserve online as an e-book and in Uris Library as a hard copyD. M. Harris and S. L. Harris Digital Design and Computer architecture 2nd edition, Morgan Kaufmann, 2012 Cornell bookstore (new: $90, used: $56), Amazon ($63)On reserve online as an e-book and in Uris Library as a hard 4750 Computer architecture , fall 2020 Course Syllabus2. DescriptionThis Course aims to provide a strong foundation for students to understand modern Computer sys-tem architecture and to apply these insights and principles to future Computer designs. The courseis structured around the three primary building blocks of general-purpose computing systems: pro-cessors, memories, and first half of the Course focuses on the fundamentals of each building block.

3 Topics includeinstruction set architecture ; single-cycle, FSM, and pipelined processor microarchitecture; direct-mapped vs. set-associative cache memories; memory protection, translation, and virtualization; FSMand pipelined cache microarchitecture; cache optimizations; network topology and routing; buffer,channel, and router microachitecture; and integrating processors, memories, and networks. Thesecond half of the Course delves into more advanced techniques and will enable students to under-stand how these three building blocks can be integrated to build a modern shared-memory multicoresystem. Topics include superscalar execution, out-of-order execution, register renaming, memorydisambiguation, branch prediction, and speculative execution; multithreaded, VLIW, and SIMD pro-cessors; non-blocking cache memories; and memory synchronization, consistency, and will learn how to evaluate design decisions in the context of past, current, and future appli-cation requirements and technology Course includes a significant project decomposed into five lab assignments.

4 Throughout thesemester, students will gradually design, implement, test, and evaluate a complete multicore systemcapable of running simple parallel applications at the register-transfer ObjectivesThis Course is meant to be a capstone Course in Computer engineering that draws together conceptsfrom across the ECE curriculum including digital logic design, Computer organization , system-levelsoftware, and engineering design. The Course will prepare students for jobs in the Computer engi-neering industry and can act as a springboard to more advanced material in graduate-level Course can also provide a foundation for students interested in performance programming,compilers, and operating systems; and it can provide system-level context for students interested inemerging technologies and digital circuits.

5 By the end of this Course , students should be able to: describecomputer architecture concepts and mechanisms related to the design of modernprocessors, memories, and networks and explain how these concepts and mechanisms interact. applythis understanding to new Computer architecture design problems within the context ofbalancing application requirements against technology constraints; more specifically,quantitatively assess a design s execution time in cycles and qualitatively assess a design scycle time, area, and energy. evaluatevarious design alternatives and make a compelling quantitative and/or qualitativeargument for why one design is superior to the other approaches. demonstratethe ability to implement and verify designs of varying complexity at theregister-transfer-level. createnew designs at the register-transfer-level and the associated effective testing strategies.

6 Writeconcise yet comprehensive technical reports that describe designs implemented at theregister-transfer-level, explain the testing strategy used to verify functionality, and evaluate thedesigns to determine the superior 4750 Computer architecture , fall 2020 Course Syllabus4. PrerequisitesThis Course is targeted towards senior-level undergraduate students, although it is also appropriatefor advanced juniors, , and first-year students. An introductory Course on computingis required (CS 1110 or equivalent). A Course in digital logic design and Computer organization (ECE 2300 or equivalent) and a Course in system-level programming (ECE 3140 or equivalent) arealso required. CS 3410 is a suitable replacement for ECE 2300 and ECE 3140 for the purposes ofsatisfying the prerequisites.

7 Students should feel comfortable working with a hardware descriptionlanguage such as Verilog, SystemVerilog, or VHDL and have a reasonable understanding of digitallogic, assembly-level programming, storage systems, basic pipelining, and simple cache and students coming from undergraduate institutions other than Cornell may wantto spend additional time reviewing the secondary required textbook, Digital Design and ComputerArchitecture, 2nd edition by D. M. Harris and S. L. Harris (Morgan Kaufmann, 2012), to refresh theirunderstanding of basic concepts. Students who have never used Python before may want to spendadditional time reviewing the optional textbook titled Think Python: How to Think Like a ComputerScientist by A. B. Downey (Green Tea Press, 2014). Students are not required to use the Veriloghardware description language for the lab assignments.

8 If a student has less experience workingwith Verilog but still wants to use this language, then they are strongly encouraged to read Chapter 4in Harris and Harris on digital design with Verilog and/or to review the optional text Verilog HDL:A Guide to Digital Design and Synthesis, 2nd edition by S. Palnitkar (Prentice Hall, 2003). Studentsshould also plan to attend the optional discussion sections, which will cover the basics of the Pythonand Verilog hardware modeling TopicsThe Course includes four parts: the first two parts cover the fundamentals of processor, memory,and network design, while the final two parts cover more advanced processor and memory addition, the final lecture at the end of the Course will present in detail an example architecturefrom industry to help illustrate the concepts discussed in class.

9 A tentative list of topics for eachpart is included below. The exact topics covered in the Course are subject to change based on studentprogress and interest. Part 1: Fundamental Processors (5 lectures) instruction set architecture ; single-cycle, FSM,and pipelined processor microarchitecture; resolving structural, data, control, and namehazards; and analyzing processor performance Part 2: Fundamental Memories (4 lectures) memory technology; direct-mappedvs. associative caches; write-through vs write-back caches; memory protection, translation, andvirtualization; FSM and pipelined cache microarchitecture; analyzing memory performance;and integrating processors and memories Part 3: Advanced Processors (10 lectures) superscalar execution, out-of-order execution,register renaming, memory disambiguation, branch prediction, speculative execution;multithreaded, VLIW, and SIMD processors Part 4: Advanced Memories (2 lectures) advanced cache microarchitecture; memorysynchronization, consistency, and coherence3 ECE 4750 Computer architecture , fall 2020 Course Syllabus6.

10 Required MaterialsThere are two materials that students are required to have access to for the Course : the primary coursetextbook, and the secondary Course textbook. Note that if students are unsure about whether or notthey will enroll in the class, they should be able to delay purchasing these items until the second orthird week of class without significantly hindering their progress in the Course . These materials areon reserve at Uris Library and/or available online to Cornell students. Hennessy and Patterson Textbook The primary required textbook for the Course is ComputerArchitecture: A Quantitative Approach, 5th ed., by J. L. Hennessy and D. A. Patterson (MorganKaufmann, 2012). This is the classic text in the field, recently updated in 2012. The first chap-ter will be available on the Course website for download.