Enhanced Serial Peripheral Interface (eSPI)

1 327432-002 Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms) January 2016 Revision 2 327432-004 Inte l he reby grants yo u a fully-paid, non-exclusive, non-transferable, w orldwide, limited license (w ithout the right to sublicense), under its copyrights to view, download, and reproduce the Enhanced Serial Peripheral Interface (eSPI) Specification ("Specification"). You are not granted any other rights or licenses, by implication, estoppel, or otherwise, and you may not create any derivative w orks of the Specification.

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7 Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting Intel, the Intel logo, and Xeon are trademarks of Intel Corporation in the and/or other countries. *Other names and brands may be claimed as the property of others. Copyright 2016, Intel Corporation. All Rights Reserved * Other names and brands may be claimed as the property of others. Copyright 2016, Intel Corporation. All rights reserved. 327432-004 3 Contents 1 8 2 Introduct ion.

8 9 Requirements .. 12 3 Architecture Overview .. 14 System Topology .. 14 Architecture Descriptions .. 18 Pin Descript ions .. 22 4 Bus Protocol .. 24 Basic Protocol .. 24 Command Phase .. 28 Turn-Around (TAR) .. 33 Response Phase .. 34 Response .. 34 Status .. 36 Ale rt Phase .. 39 Get Status 42 Get Configurat ion and Set Configurat ion Command .. 43 Non-Posted Transaction .. 44 Posted Transaction .. 49 WAIT STATE .. 51 5 Transaction Layer .. 53 Cycle Types and Packet 53 Cycle 54 Tag.

9 57 Length .. 57 58 59 Channels .. 59 Peripheral Channel .. 59 Virtual Wires Channel .. 66 OOB (Tunneled SMBus) Message Channel .. 82 Run-time Flash Access Channel .. 85 Slave Buffer Management .. 89 Transact io n Orde r ing R u 91 Zero Length Read and Write .. 92 6 Link Layer .. 93 Single I/O, Dual I/O and Quad I/O Modes .. 93 4 327432-004 Cyclic Redundancy Check (CRC).. 97 7 Slave Registers .. 99 Status Register .. 99 C apabilit ies and C o nfig urat io n Reg isters.

10 100 8 Operat ing Spec if icat io 111 E lectr ica l S pecif icat io n .. 111 Tim ing 112 9 System Architecture .. 115 Interrupts .. 115 Error Detection and Handling .. 115 Slave s Detected Errors .. 116 Master s Detected Errors .. 124 127 eSPI Reset# .. 127 In-band RESET Command .. 128 Power Management Event (PME) .. 129 Pow er Sequenc ing & In it ia liz atio 129 Exit fro m 129 Figures Figure 1: EC/BMC/SIO Communicat ion over LPC .. 10 Figure 2: EC/BMC/SIO Communicat ion over 11 Fig ure 3: Examp le o f LPC b us a nd A dd it io na l eSP I b us be h in d the eSP I.