External Memory Interfaces Intel® Stratix® 10 FPGA IP User ...

1 External Memory Interfaces Intel Stratix 10 FPGA IP User GuideUpdated for Intel Quartus Prime Design Suite: Version: FeedbackUG-S10 EMI | document on the web: PDF | HTMLC ontents1. Release 82. External Memory Interfaces Intel Stratix 10 FPGA IP Intel Stratix 10 EMIF IP Design Intel Stratix 10 EMIF IP Design Intel Stratix 10 EMIF IP Product Intel Stratix 10 EMIF Architecture: Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: Input DQS Clock Intel Stratix 10 EMIF Architecture: PHY Clock Intel Stratix 10 EMIF Architecture.

2 PLL Reference Clock Intel Stratix 10 EMIF Architecture: Clock Phase Intel Stratix 10 EMIF Intel Stratix 10 EMIF DQS Intel Stratix 10 EMIF Intel Stratix 10 Calibration Stages .. Intel Stratix 10 Calibration Stages Intel Stratix 10 Calibration Intel Stratix 10 Calibration Intel Stratix 10 EMIF IP Hard Memory Intel Stratix 10 Hard Memory Controller Rate Conversion Hardware Resource Sharing Among Multiple Intel Stratix 10 I/O SSM I/O Bank PLL Reference Clock Core Clock Network User-requested Reset in Intel Stratix 10 EMIF Intel Stratix 10 EMIF for Hard Processor Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with Using the Legacy EMIF Debug Toolkit with Intel Stratix 10 HPS HPS

3 EMIF Intel Stratix 10 EMIF Ping Pong Intel Stratix 10 Ping Pong PHY Feature Intel Stratix 10 Ping Pong PHY Intel Stratix 10 Ping Pong PHY Intel Stratix 10 Ping Pong PHY Using the Ping Pong Ping Pong PHY Simulation Example 494. Intel Stratix 10 EMIF IP End-User Interface and Signal Intel Stratix 10 EMIF IP Interfaces for Memory Interfaces Intel Stratix 10 FPGA IP User GuideSend Intel Stratix 10 EMIF IP Interfaces for Intel Stratix 10 EMIF IP Interfaces for QDR II/II+/II+ Intel Stratix 10 EMIF IP Interfaces for Intel Stratix 10 EMIF IP Interfaces for RLDRAM AFI AFI Clock and Reset AFI Address and Command AFI Write Data AFI Read Data AFI Calibration Status AFI Shadow Register Management AFI Timing AFI Address and Command Timing

4 AFI Write Sequence Timing AFI Read Sequence Timing AFI Calibration Status Timing Intel Stratix 10 Memory Mapped Register (MMR) ecc3: ECC Error and Interrupt ecc4: Status and Error ecc5: Address of Most Recent ecc6: Address of Most Recent Correction Command ecc7: Extension for Address of Most Recent ecc8: Extension for Address of Most Recent Correction Command Intel Stratix 10 EMIF Simulating Memory Simulation HPS EMIF FeedbackExternal Memory Interfaces Intel Stratix 10 FPGA IP User Simulation Calibration Abstract PHY Simulation Functional Simulation with Verilog Functional Simulation with Simulating the Design Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: FPGA Intel Stratix 10 EMIF IP DDR3 Parameters.

5 Intel Stratix 10 EMIF IP DDR3 Parameters: Mem Intel Stratix 10 EMIF IP DDR3 Parameters: Mem Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Example Board Skew Equations for DDR3 Board Skew Pin and Resource Interface FPGA Pin Guidelines for Intel Stratix 10 EMIF DDR3 Board Design Terminations and Slew Rates with Intel Stratix 10 Channel Signal Integrity Layout Design Layout Package 1917.

6 Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: FPGA Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Mem Intel Stratix 10 EMIF IP DDR4 Parameters: Mem Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Example Board Skew Equations for DDR4 Board Skew Pin and Resource Interface FPGA Pin Guidelines for Intel Stratix 10 EMIF Resource Sharing Guidelines (Multiple Interfaces ).

7 DDR4 Board Design Memory Interfaces Intel Stratix 10 FPGA IP User GuideSend Terminations and Slew Rates with Intel Stratix 10 Channel Signal Integrity Layout Design Layout Package 2528. Intel Stratix 10 EMIF IP for QDR II/II+/II+ Parameter Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGA Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters.

8 Board Skew Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Pin and Resource Interface QDR II/II+/II+ Xtreme Board Design QDR II SRAM General Layout QDR II Layout QDR II SRAM Layout Package Package Slew Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: FPGA Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Mem Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Example Board Skew Equations for QDR-IV Board Skew Pin and Resource Interface QDR-IV Board Design QDR-IV Layout General Layout QDR-IV Layout Package Package Slew FeedbackExternal Memory Interfaces Intel Stratix 10 FPGA IP User Guide510.

9 Intel Stratix 10 EMIF IP for RLDRAM Parameter Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: FPGA Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Mem Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Example Board Skew Equations for RLDRAM 3 Board Skew Pin and Resource Interface RLDRAM 3 Board Design RLDRAM 3 General Layout RLDRAM 3 Layout Layout Package Package Slew 34511.

10 Intel Stratix 10 EMIF IP Timing Timing Closure .. Timing Timing Report Optimizing Early I/O Timing Performing Early I/O Timing 35512. Optimizing Controller Interface Bank Management Data Improving Controller Auto-Precharge Bank Additive Latency and Bank User-Controlled Frequency of Series of Reads or Data Starvation Command Enable Command Priority Intel Stratix 10 EMIF IP Interface Configuration Performance 376 ContentsExternal Memory Interfaces Intel Stratix 10 FPGA IP User GuideSend Interface Configuration Bottleneck and Efficiency Functional Issue Intel IP Memory Vendor Memory Transcript Window Modifying the Example