High Definition Audio Specification - Intel

1 high Definition Audio Specification Revision June 17, 2010 Revision History Revision Purpose Date Initial Release April 15, 2004 Updated with DCN No: HDA001-A changes. Updated with DCN No: HDA002-A changes. Updated with DCN No: HDA006-A changes. Updated with DCN No: HDA011-A changes. Updated with DCN No: HDA012-A changes. Updated with DCN No: HDA015-B changes. Updated with DCN No: HDA016-A changes. Updated with DCN No: HDA017-A changes. Updated with DCN No: HDA019-A changes. Updated with DCN No: HDA022-A changes. Updated with DCN No: HDA024-A changes. Updated with DCN No: HDA034-A2 changes. Updated with DCN No: HDA035-A changes. Updated with DCN No: HDA036-A changes. Updated with DCN No: HDA039-A changes. Updated with DCN No: HDA041-A changes. Updated with DCN No: HDA042-A changes. Errata: Clarified Input Payload Capability and Output Payload Capability Reset value is implementation specific. Clarified that Stream Descriptor n FIFO Size must be valid and static after every programming of data format register, as well as when RUN bit is set.

2 Clarified that Stream Descriptor n BDL Pointer Upper Base Address register attribute is RO if not supporting 64 bit addressing. Fixed timing error in Codec Discovery section that SW should wait for at least 521 us (25 frames) after reading CRST# as 1 before accessing codec. Strongly recommend the default value for EAPD to be 1 in EAPD/BTL Enable section. Clarified the codec response expected for double Function Group reset command in D3cold state, but recommended no response for the first Function Group reset of the double Function Group reset command sequence. Clarified the reset value for FIFOS register is implementation specific. Clarified UR enable verb for function group node is conditional in the required support for verbs table. June 17, 2010 Legal Notice THIS Specification IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, Specification OR SAMPLE.

3 Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this Specification . No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein, except that a license is hereby granted to copy and reproduce this Specification for internal use only. Intel assumes no responsibility for any errors contained in this document and has no liabilities or obligations for any damages arising from or in connection with the use of this document. Intel may make changes to specifications, product descriptions, and plans at any time, without notice. Intel may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

4 *Other names and brands may be claimed as the property of others. Copyright 2003-2010, Intel Corporation. All rights reserved. Rev. high Definition Audio Specification iii Contents 1 Introduction .. 16 Scope and Layout of This Document .. 16 Motivation and Goals .. 16 AC 97 Compatibility .. 17 Feature List .. 17 Related Documents .. 17 2 Architecture Overview .. 18 Hardware System Overview .. 18 Streams and Channels .. 19 DMA Channel Operation .. 21 Initialization and Enumeration .. 22 3 Register Interface .. 24 Introduction to Controller Registers .. 24 Terminology .. 24 General Register Behaviors and Access Requirements .. 24 Behavior With 64-bit Addresses .. 25 high Definition Audio Controller System Bus Interface Registers .. 25 high Definition Audio Controller Register Set .. 25 Global Capabilities, Status, and Control .. 28 Offset 00h: GCAP Global Capabilities.

5 28 Offset 02h: VMIN Minor Version .. 29 Offset 03h: VMAJ Major Version .. 29 Offset 04h: OUTPAY Output Payload Capability .. 29 Offset 06h: INPAY Input Payload Capability .. 30 Offset 08h: GCTL Global Control .. 30 Offset 0Ch: WAKEEN Wake Enable .. 31 Offset 0Eh: STATESTS State Change Status .. 32 Offset 10h: GSTS Global Status .. 32 Offset 18h: OUTSTRMPAY Output Stream Payload Capability .. 32 Offset 1Ah: INSTRMPAY Input Stream Payload Capability .. 33 Interrupt Status and Control .. 33 Offset 20h: INTCTL Interrupt Control .. 34 Offset 24h: INTSTS Interrupt Status .. 35 Offset 30h: Wall Clock Counter .. 35 Offset 38h: SSYNC Stream Synchronization .. 36 Offset 40h: CORB Lower Base Address .. 36 Offset 44h: CORBUBASE CORB Upper Base Address .. 36 Offset 48h: CORBWP CORB Write Pointer .. 37 Offset 4Ah: CORBRP CORB Read Pointer .. 37 Offset 4Ch: CORBCTL CORB Control.

6 37 Offset 4Dh: CORBSTS CORB Status .. 38 Offset 4Eh: CORBSIZE CORB Size .. 38 Offset 50h: RIRBLBASE RIRB Lower Base Address .. 39 high Definition Audio Specification Rev. iv Offset 54h: RIRBUBASE RIRB Upper Base Address .. 39 Offset 58h: RIRBWP RIRB Write Pointer .. 39 Offset 5Ah: RINTCNT Response Interrupt Count .. 40 Offset 5Ch: RIRBCTL RIRB Control .. 40 Offset 5Dh: RIRBSTS RIRB Status .. 41 Offset 5Eh: RIRBSIZE RIRB Size .. 41 Offset 70h: DPLBASE DMA Position Lower Base Address .. 42 Offset 74h: DPUBASE DMA Position Upper Base Address .. 43 Stream Descriptors .. 43 Offset 80: {IOB}SDnCTL Input/Output/Bidirectional Stream Descriptor n Control .. 43 Offset 83h: {IOB}SD0 STS Input/Output/Bidirectional Stream Descriptor n Status .. 45 Offset 84: {IOB}SDnLPIB Input/Output/Bidirectional Stream Descriptor n Link Position in Buffer .. 46 Offset 88: {IOB}SDnCBL Input/Output/Bidirectional Stream Descriptor n Cyclic Buffer Length.

7 46 Offset 8C: {IOB}ISDnLVI Input/Output/Bidirectional Stream Descriptor n Last Valid 47 Offset 90: {IOB}SDnFIFOS Input/Output/Bidirectional Stream Descriptor n FIFO Size .. 47 Offset 92: {IOB}SDnFMT Input/Output/Bidirectional Stream Descriptor n Format .. 47 Offset 98h: {IOB}SDnBDPL Input/Output/Bidirectional Stream Descriptor n BDL Pointer Lower Base Address .. 49 Offset 9Ch: {IOB}SDnBDPU Input/Output/Bidirectional Stream Descriptor n BDL Pointer Upper Base Address .. 49 Offset 2030h: WALCLKA Wall Clock Counter Alias .. 49 Offset 2084, 20A4, ..: {IOB}SDnLICBA Input/Output/Bidirectional Stream Descriptor n Link Position in Buffer Alias .. 50 Immediate Command Input and Output Registers .. 50 Offset 60h: Immediate Command Output Interface .. 50 Offset 64h: Immediate Response Input Interface .. 50 Offset 68h: Immediate Command Status .. 52 Interrupt Structure .. 53 Data Structures.

8 55 DMA Position in Current Buffer .. 55 Buffer Descriptor List .. 55 Buffer Descriptor List Entry .. 55 Command Output Ring Buffer .. 56 Response Input Ring Buffer .. 56 Codec Verb and Response 57 Stream Format Structure .. 58 4 Programming Model .. 61 Theory of Operation .. 61 Controller Initialization .. 61 Configuring a PCI or PCI Express Interface .. 61 Starting the high Definition Audio Controller .. 61 Rev. high Definition Audio Specification v Codec Discovery .. 62 Codec Command and Control .. 62 Command Outbound Ring Buffer CORB .. 62 CORB Buffer Allocation .. 64 CORB Entry Format .. 64 Initializing the CORB .. 64 Transmitting Commands via the CORB .. 65 Other CORB Programming Notes .. 66 Response Inbound Ring Buffer - RIRB .. 66 RIRB Entry Format:.. 67 Initializing the 68 Stream Management .. 69 Stream Data In Memory .. 69 Configuring and Controlling Streams.

9 70 Starting Streams .. 70 Stopping Streams .. 71 Resuming Streams .. 71 Stream Steady State Operation .. 71 72 Controller to Controller Synchronization .. 72 Stream to Stream Start Synchronization .. 72 Stream to Stream Stop Synchronization .. 73 Power Management .. 73 Power State Transitions .. 73 Power Optimization .. 73 Codec Wake .. 74 Codec Wake From System S0, Controller D0 .. 74 Codec Wake From System S0, Controller D3 .. 74 Codec Wake From System S3 .. 74 Checking Wake Status on Resume .. 74 5 Link Protocol .. 77 Introduction .. 77 Link Signaling .. 77 Signal Definitions .. 77 Signaling Topology .. 78 Basic System .. 78 Bandwidth Scaling .. 79 Relative Signal 80 Frame Composition .. 83 Basic Frame Components .. 83 Output Frame Formatting .. 85 Outbound Stream Tags .. 85 Outbound Frame Overview Single SDO .. 86 Outbound Frame Overview Multiple SDO.

10 87 Input Frame Formatting .. 88 Inbound Stream Tags .. 88 Zero Padding Inbound Stream Packets .. 89 Inbound Frame Overview .. 90 high Definition Audio Specification Rev. vi Stream Transmission Over Multiple SDI Signals .. 90 Handling Stream Independent Sample Rates .. 91 Codec Sample Rendering Timing .. 91 Link Sample Delivery Timing .. 92 Source Synchronous Input .. 94 Reset and Initialization .. 95 Link Reset .. 95 Entering Link 95 Exiting Link Reset .. 96 Codec Function Group Reset .. 97 Codec Initialization .. 97 Connect and Turnaround Frames .. 98 Address Frame .. 99 Multi-SDI Codec Initialization .. 101 Un-initialized and Partially Initialized Codecs .. 101 Power Management .. 101 6 Electrical Interface .. 105 Overview .. 105 to Low Voltage ( ) Transition .. 105 Signaling Environment .. 105 DC Specifications .. 105 AC Specifications .. 106 Maximum AC Ratings and Device Protection.