Transcription of Intel Ethernet Controller X550
1 Revision 2017333369-004 Intel Ethernet Controller x550 DatasheetEthernet Networking Division (ND)PRODUCT FEATURESG eneral Serial Flash interface Configurable LED operation for software or customizing OEM LED displays Device disable capability Package size - 25 mm x 25 mm ( x550 -BT2) Package size - 17 mm x 17 mm ( x550 -AT2)Networking 10 GbE/1 GbE/100 Mb/s copper PHYs integrated on-chip Support for jumbo frames of up to KB Flow control support: send/receive pause frames and receive FIFO thresholds Statistics for management and RMON VLAN support TCP segmentation offload: up to 256 KB IPv6 support for IP/TCP and IP/UDP receive checksum offload Fragmented UDP checksum offload for packet reassembly Message Signaled Interrupts (MSI) Message Signaled Interrupts (MSI-X) Interrupt throttling control to limit maximum interrupt rate and improve CPU usage Flow Director (16 x 8 and 32 x 4) 128 transmit queues Receive packet split header Receive header replication Dynamic interrupt moderation TCP timer interrupts Relaxed ordering Support for 64 virtual machines per port (64 VMs x 2 queues) Support for Data Center Bridging (DCB).
2 ( , , )Host Interface PCIe Base Specification Bus width x1, x4, x8 64-bit address support for systems using more than 4 GB of physical memory MAC FUNCTIONS Descriptor ring management hardware for transmit and receive ACPI register set and power down functionality supporting D0 and D3 states A mechanism for delaying/reducing transmit interrupts Software-controlled global reset bit (resets everything except the configuration registers) Four Software-Definable Pins (SDP) per port Wake up IPv6 wake-up filters Configurable flexible filter (through NVM) LAN function disable capability Programmable memory transmit buffers (160 KB/port) Default configuration by NVM for all LEDs for pre-driver functionalityManageability SR-IOV support Eight VLAN L2 filters 16 Flex L3 port filters Four Flexible TCO filters Four L3 address filters (IPv4) Advanced pass through-compatible management packet transmit/receive support SMBus interface to an external Manageability Controller (MC) NC-SI interface to an external MC Four L3 address filters (IPv6) Four L2 address filtersIntel Ethernet Controller x550 Datasheet Revision History2333369-004 Revision 21, 2017 Updates include the following: Added Section , Pin Differences in the x550 -AT Single Port Device.
3 Section Added reference to list of support message types. Section Modified verbiage in Value column for Bytes 3:5 in Table 11-44. Section Added new table for x550 -AT power consumption. Section Updated values in associate 10, 2016 Updates include the following: Removed bit. No longer used for triggering Shadow RAM dump. Removed FLUPDATE register (0x00015F54). Ta b l e 3 - 2 5 Updated description for SDP1. Section , Link Capabilities Register (0xAC; RO) Changed default value for ASPM support (bits 11:10) to 10b. Section , Driver Info Host Command Updated Table 11-49. Table 12-3 and Table 12-4 Changed Device Total Power units from mW to W. Table 12-20 Updated thermal diode typical ESR value to . Table 15-2 Updated ID Code values.
4 Other miscellaneous 8, 2016 Updates include the following: Updated PHY Registers section. Changed Max temperature in NVM mode to 102 (Tjunction max changed 107). Added NBASE-T information. Removed 10 BASE-T information. Removed x2 lane width. Updated power numbers. Updated heat sink and other thermal There were no previous versions of this document 27, 2015 Initial release ( Intel public)333369-0043 Contents Intel Ethernet Controller x550 Introduction .. Overview .. Configurations .. Interfaces .. Interface .. Interfaces .. Flash Interface .. Interface .. Pins (SDP) Interface (General-Purpose I/O).. Interface .. Summary .. : New Capabilities Beyond the X540 .. Support .. Capabilities .. 1588.
5 And Acronyms .. Ordering .. and Basic Operation .. (Tx) Data (Rx) Data Flow .. Pin Interface .. Type Definition .. Assignments .. Flash .. Defined Pins (SDPs) .. and No-Connect .. Supplies .. Information .. Options .. Out Top View Through Package .. Interconnects .. Express (PCIe) .. 50 Intel Ethernet Controller x550 Datasheet Layer .. Events and Error and Statistics Counters .. Interfaces .. Controller Sideband Interface (NC-SI) .. Characteristics .. Transactions .. (Over PCIe or SMBus) .. Memory (NVM) .. RAM .. Clients and Access Contention .. Field .. Read, Write, and Erase Sequences .. NVM Flows .. Authentication Procedure.
6 I/O Pins Software-Definable Pins (SDPs) .. Over SDP .. Interface .. MDIO Interface .. Copper PHY Functionality .. Flow Control (FC) .. Packet Gap (IPG) Control and Initialization .. Up .. Sequence .. Timing Diagram .. Operation .. Operation .. in PCI-IOV Environment .. Effects .. Disable .. Disable .. Flow for Enable/Disable Disable .. Disable of the Device at Boot Time by Using the Strapping Option .. Initialization and Diagnostics .. State .. 140333369-0045 Contents Intel Ethernet Controller x550 Sequence .. Mb/s, 1 GbE, and 10 GbE Link Initialization .. of Statistics .. Initialization .. Initialization Flow .. Initialization Flow .. Initialization.
7 MAC Address to Shared Resources .. Power Management and Delivery .. Targets and Power Delivery .. Management .. to x550 Power States .. Power Usage .. Link Power Management .. States .. of Power-State Transitions .. Interfaces Power Management .. Power-Down State .. Power-Down via the PHY Register .. Power-Down (SPD) .. 10 GBASE-T and/or 1000 BASE-T Speeds .. Power Link Up (LPLU) .. Efficient Ethernet (EEE) .. Power Management Wake-Up .. Power Management Wake-Up .. Packets .. and Virtualization .. Coalescing .. Coalescing Coalescing Operating Mode .. Coalescing Recommended .. Initialization Flow .. Management .. Mode .. Mode .. Sensor Control .. Sensor Characteristics.
8 Non-Volatile Memory Map .. Organization .. Areas .. Header .. Sections .. 207 Intel Ethernet Controller x550 Datasheet Compatibility Module Word Address 0x10-0x14 .. Number Module Word Address 0x15-0x16 .. Configuration Block Word Address 0x17 .. Reserved Words Module Pointer Word Address 0x2F .. Configuration Words Word Address 0x30-0x36 .. Ethernet MAC Address Pointer Word Address 0x37 .. Scratch Pad Pointer Word Address Sections .. Section Auto-Load Sequence .. Init Module .. Analog Configuration Module .. Link Configuration Module .. General Configuration Module .. Configuration Space 0/1 Modules .. Core 0/1 Modules .. 0/1 Auto Configuration Auto Configuration Module.
9 Sections .. Module Firmware Parameters Module Global MNG Offset 0x2 .. LAN 0/1 Configuration Modules Global MNG Offsets 0x03 and 0x06 .. Configuration Module Global MNG Offset 0x04 .. TCO Filter Configuration Module Global MNG Offset 0x05 .. Loader Module .. Image Expansion/Option ROM .. Module .. Provisional Inline Functions .. Functionality .. Layer - Filtering .. Queues Assignment .. Data Storage in System Memory .. Descriptors .. Offloads .. Statistics .. Functionality .. Transmission .. Contexts .. Descriptors .. and UDP Segmentation .. Checksum Offloading in Non-Segmentation Mode .. Statistics .. Registers .. Moderation .. Timer of Interrupt 352333369-0047 Contents Intel Ethernet Controller x550 VLAN Support.
10 VLAN Packet Format .. Tagged Frames .. and Receiving Packets .. VLAN Packet Filtering .. VLAN and Single VLAN Support .. and VLAN .. Processing Hints (TPH) .. Tag and Processing Hint Center Bridging (DCB) .. Capabilities .. SYNC (IEEE1588 and ) .. and Hardware/Software Responsibilities .. Time Sync Elements .. Time Sync Elements .. Sync Interrupts .. Packet Structure .. SR-IOV Support .. Features .. of Hardware .. Support .. Side Coalescing (RSC) .. Candidacy for RSC .. Identification and RSC Context Matching .. New RSC .. Active RSC .. DMA and Descriptor Write Completion and Aging .. Channel over Ethernet (FCoE) .. Transmit Receive Operation .. Integrity Protection.
