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INTRODUCTION TO DELTA-SIGMA ADCS

ECE1371 Advanced Analog Circuits Lecture 1. INTRODUCTION TO. DELTA-SIGMA ADCS. Richard Schreier Trevor Caldwell Course Goals Deepen understanding of CMOS analog circuit design through a top-down study of a modern analog system The lectures will focus on DELTA-SIGMA ADCs, but you may do your project on another analog system. Develop circuit insight through brief peeks at some nifty little circuits The circuit world is filled with many little gems that every competent designer ought to recognize. ECE1371 1-2. Logistics Format: Meet Mondays 3:00-5:00 PM. except Feb 4 and Feb 18. 12 2-hr lectures plus proj. presentation Grading: 40% homework 60% project References: Schreier & Temes, Understanding . Johns & Martin, Analog IC Design . Razavi, Design of Analog CMOS ICs . Lecture Plan: ECE1371 1-3. Date Lecture Ref Homework 2008-01-07 RS 1 INTRODUCTION : MOD1 & MOD2 S&T 2-3, A Matlab MOD2. 2008-01-14 RS 2 Example Design: Part 1 S&T , J&M 10 Switch-level sim 2008-01-21 RS 3 Example Design: Part 2 J&M 14 Q-level sim 2008-01-28 TC 4 Pipeline and SAR ADCs Arch.

DELTA-SIGMA ADCS Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca ECE1371 1-2 Course Goals • Deepen understanding of CMOS analog circuit design through a top-down study of a modern analog system The lectures will focus on Delta-Sigma ADCs, but you may do your project on another analog system.

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Transcription of INTRODUCTION TO DELTA-SIGMA ADCS

1 ECE1371 Advanced Analog Circuits Lecture 1. INTRODUCTION TO. DELTA-SIGMA ADCS. Richard Schreier Trevor Caldwell Course Goals Deepen understanding of CMOS analog circuit design through a top-down study of a modern analog system The lectures will focus on DELTA-SIGMA ADCs, but you may do your project on another analog system. Develop circuit insight through brief peeks at some nifty little circuits The circuit world is filled with many little gems that every competent designer ought to recognize. ECE1371 1-2. Logistics Format: Meet Mondays 3:00-5:00 PM. except Feb 4 and Feb 18. 12 2-hr lectures plus proj. presentation Grading: 40% homework 60% project References: Schreier & Temes, Understanding . Johns & Martin, Analog IC Design . Razavi, Design of Analog CMOS ICs . Lecture Plan: ECE1371 1-3. Date Lecture Ref Homework 2008-01-07 RS 1 INTRODUCTION : MOD1 & MOD2 S&T 2-3, A Matlab MOD2. 2008-01-14 RS 2 Example Design: Part 1 S&T , J&M 10 Switch-level sim 2008-01-21 RS 3 Example Design: Part 2 J&M 14 Q-level sim 2008-01-28 TC 4 Pipeline and SAR ADCs Arch.

2 Comp. 2008-02-04 ISSCC No Lecture 2008-02-11 RS 5 Advanced S&T 4, , , B CTMOD2; Proj. 2008-02-18 Reading Week No Lecture 2008-02-25 RS 6 Comparator & Flash ADC J&M 7. 2008-03-03 TC 7 SC Circuits J&M 10. 2008-03-10 TC 8 Amplifier Design 2008-03-17 TC 9 Amplifier Design 2008-03-24 TC 10 Noise in SC Circuits S&T C. 2008-03-31 Project Presentation 2008-04-07 TC 11 Matching & MM-Shaping Project Report 2008-04-14 RS 12 Switching Regulator Q-level sim ECE1371 1-4. NLCOTD: Level Translator VDD1 > VDD2, 3-V logic ? 1-V logic VDD1 < VDD2, 1-V logic ? 3-V logic Constraints: CMOS. 1-V and 3-V devices no static current ECE1371 1-5. What is ? is NOT a fraternity It is more like a way of life . Simplified ADC structure: Analog Loop Coarse Digital In Filter ADC Out (to digital filter). DAC. Key features: coarse quantization, filtering, feedback and oversampling Quantization is often quite coarse: 1 bit! ECE1371 1-6. What is Oversampling? Oversampling is sampling faster than required by the Nyquist criterion For a lowpass signal containing energy in the frequency range ( 0, f B ) , the minimum sample rate required for perfect reconstruction is f s = 2f B.

3 The oversampling ratio is OSR f s ( 2f B ). For a regular ADC, OSR 2 3. To make the anti-alias filter (AAF) feasible For a ADC, OSR 30. To get adequate quantization noise suppression. All signals above f B are removed digitally. ECE1371 1-7. Oversampling Simplifies AAF. Desired Undesired OSR ~ 1: Signal Signals f fs 2 First alias band is very close OSR = 3: Wide transition band f fs 2 Alias far away ECE1371 1-8. How Does A ADC Work? Coarse quantization lots of quantization error. So how can a ADC achieve 22-bit resolution? A ADC spectrally separates the quantization error from the signal through noise-shaping 1. t t 1. analog u v Decimation w digital input ADC Filter n@2f output 1 bit @fs B. desired signal Nyquist-rate undesired shaped signals noise PCM Data fB fs 2 fB fs 2 fB. ECE1371 1-9. A DAC System 1. t 1. digital u v Reconstruction w analog input Modulator Filter output (interpolated) 1 bit @fs analog signal shaped output noise fB fs 2 fB fs 2 fB fs Mathematically similar to an ADC system Except that now the modulator is digital and drives a low-resolution DAC, and that the out-of-band noise is handled by an analog reconstruction filter.

4 ECE1371 1-10. Why Do It The Way? ADC: Simplified Anti-Alias Filter Since the input is oversampled, only very high frequencies alias to the passband. These can often be removed with a simple RC section. If a continuous-time loop filter is used, the anti-alias filter can often be eliminated altogether. DAC: Simplified Reconstruction Filter The nearby images present in Nyquist-rate reconstruction can be removed digitally. + Inherent Linearity Simple structures can yield very high SNR. + Robust Implementation tolerates sizable component errors. ECE1371 1-11. Highlights ( What you will learn today). 1 1st- and 2nd-order modulator structures and theory of operation 2 Inherent linearity of binary modulators 3 Inherent anti-aliasing of continuous-time modulators 4 Spectrum estimation with FFTs ECE1371 1-12. Background (Stuff you already know). The SQNR* of an ideal n-bit ADC with a full-scale sine-wave input is ( + ) dB. 6 dB = 1 bit . The PSD at the output of a linear system is the product of the input's PSD and the squared magnitude of the system's frequency response X H(z) Y S (f ) = H (e j 2 f ) 2 S (f ).

5 Yy xx The power in any frequency band is the integral of the PSD over that band *. Signal-to-Quantization-Noise Ratio ECE1371 1-13. Poor Man's DAC. Suppose you have low-speed 16-bit data and a high-speed 8-bit DAC. How can you get good analog performance? 16-bit data 16 8 Good @ 50 kHz ? DAC Quality Audio 5 MHz ECE1371 1-14. Simple (-Minded) Solution Only connect the MSBs; leave the LSBs hanging 16 MSBs 8. DAC. @50 kHz LSBs 8. 5 MHz (or 50 kHz). 16-b Input Data DAC Output 20 us Time ECE1371 1-15. Spectral Implications Desired Signal Unwanted Images sin ( x ). ------------------ DAC frequency response x Frequency 25 kHz Quantization Noise @ 8-bit level SQNR = 50 dB. ECE1371 1-16. Better Solution Exploit oversampling: Clock fast and add dither 16 8. DAC. @50 kHz 8. 8 @ 5 MHz dither spanning 5 MHz one 8-bit LSB. DAC Output 16-b Input Data Time ECE1371 1-17. Spectral Implications Quantization noise is now spread over a broad frequency range Oversampling reduces quantization noise density MHz OSR = ---------------------- = 100 20 dB.

6 25 kHz Frequency 25 kHz MHz In-band quantization noise power = 1% of total quantization noise power SQNR = 70 dB. ECE1371 1-18. Even More Clever Method Add LSBs back into the input data 16 8. DAC. @50 kHz @ 5 MHz 8. z 1. 5 MHz DAC Output 16-b Input Data Time ECE1371 1-19. Mathematical Model Assume the DAC is ideal, model truncation as the addition of error: E = LSBs U V = U + (1 z 1)E. z-1 E. Hmm Oversampling, coarse quantization and feedback. Noise-Shaping! Truncation noise is shaped by a 1 z 1 transfer function, which provides ~35 dB of attenuation in the 0-25 kHz frequency range ECE1371 1-20. Spectral Implications Quantization noise is heavily attenuated at low frequencies Shaped Quantization Noise Frequency 25 kHz MHz In-band quantization noise power is very small, 55 dB below total power SQNR = 105 dB! ECE1371 1-21. MOD1: 1st-Order Modulator Standard Block Diagram Quantizer (1-bit) v Y 1. U Q V 1. y z-1. Feedback V' DAC v'. z-1 DAC. v Since two points define a line, a binary DAC is inherently linear.

7 ECE1371 1-22. MOD1 Analysis Exact analysis is intractable for all but the simplest inputs, so treat the quantizer as an additive noise source: Y. U Q V. z-1 E. z-1. Y V. V(z) = Y(z) + E(z). Y(z) = ( U(z) z-1V(z) ) / (1 z-1). (1 z-1) V(z) = U(z) z-1V(z) + (1 z-1)E(z). V(z) = U(z) + (1 z 1)E(z). ECE1371 1-23. The Noise Transfer Function In general, V(z) = STF(z) U(z) + NTF(z) E(z). For MOD1, NTF(z) = 1 z 1. The quantization noise has spectral shape! 4. NTF (e j 2 f ) 2. 3. 2. 1. 2 for 1. 0. 0 Normalized Frequency (f /fs). The total noise power increases, but the noise power at low frequencies is reduced ECE1371 1-24. In-band Noise Power Assume that e is white with power e2. S ee ( ) = e2 . The in-band noise power is B B. e2. N 02 =. 0. H (e j ) 2 S ee ( )d ------ . 0. 2 d . 2 e2. Since OSR ------- , N 0 = ------------- ( OSR ) 3. 2. B 3. For MOD1, an octave increase in OSR increases SQNR by 9 dB. SQNR-OSR trade-off. ECE1371 1-25. A Simulation of MOD1.

8 0. Full-scale test tone 20. SQNR = 55 dB @ OSR = 128. dBFS/NBW. 40. Shaped Noise . 60. 80 20 dB/decade NBW = 6. 100. 10 3 10 2 10 1. Normalized Frequency ECE1371 1-26. CT Implementation of MOD1. Ri/Rf sets the full-scale; C is arbitrary Also observe that an input at fs is rejected by the integrator inherent anti-aliasing Integrator Latched Comparator Rf C. Ri u y D Q v DFF. clock CK QB. ECE1371 1-27. MOD1-CT Waveforms u=0 u = 1 1. v v 1 1. y0 y0. 0 5 10 15 20 0 5 10 15 20. Time Time With u=0, v alternates between +1 and 1. With u>0, y drifts upwards; v contains consecutive +1s to counteract this drift ECE1371 1-28. Summary So Far works by spectrally separating the quantization noise from the signal Noise-shaping is achieved by the use of filtering and feedback A binary DAC is inherently linear, and thus a binary modulator is too MOD1 has NTF(z) = 1 z 1. Arbitrary accuracy for DC inputs. bit/octave SNR-OSR trade-off. MOD1-CT has inherent anti-aliasing ECE1371 1-29.

9 MOD2: 2nd-Order Modulator Replace the quantizer in MOD1 with another copy of MOD1: E1. U Q. E. V. z-1. z-1 z-1. z-1. V(z) = U(z) + (1 z 1)E1(z), E1(z) = (1 z 1)E(z). V(z) = U(z) + (1 z 1)2E(z). ECE1371 1-30. Simplified Block Diagrams E. U z 1. Q V. z 1 z 1. NTF (z ) = ( 1 z 1 ) 2. STF (z ) = z 1. E. U 1 1. Q V. z 1 z 1. -1 -2 NTF (z ) = ( 1 z 1 ) 2. STF (z ) = z 2. ECE1371 1-31. NTF Comparison 0. NTF(e j2 f ) (dB). 20. MOD1. 40. MOD2. 60. MOD2 has twice as much 80 attenuation at all frequencies 100. 10 3 10 2 10 1. Normalized Frequency ECE1371 1-32. In-band Noise Power For MOD2, H (e j ) 2 4.. B. As before, N 02 = H (e j ) 2 S ee( )d and 0. S ee( ) = e2 . 4 e2. So now N 02 = ------------- ( OSR ) 5. 5. With binary quantization to 1, = 2 and thus e2 = 2 12 = 1 3 . An octave increase in OSR increases MOD2's SNR by 15 dB ( bits) . ECE1371 1-33. Simulation Example Input at 75% of FullScale 1. Time Domain 0. 1. 0 50 100 150 200. 0. Frequency Domain Simulated Noise Density 20.

10 40. 60 Predicted Noise Density 80 Agreement is fair 1024-point FFT. 100. 0 ECE1371 1-34. Simulated MOD2 PSD. Input at 50% of FullScale 0. 20. SQNR = 86 dB. @ OSR = 128. 40. dBFS/NBW. 60 Simulated spectrum (smoothed). 80 Theoretical PSD. (k = 1). 100. 40 dB/decade 120. NBW = 10 7. 140. 10 3 10 2 10 1. Normalized Frequency ECE1371 1-35. SQNR vs. Input Amplitude MOD1 & MOD2 @ OSR = 256. 120. 100. SQNR (dB). 80. MOD2. 60. Predicted SNR. Simulated SNR. 40. MOD1. 20. 0. 100 80 60 40 20 0. Input Amplitude (dBFS). ECE1371 1-36. SQNR vs. OSR. 120. 100. MOD2. (Theoretical curve assumes -3 dBFS input). SQNR (dB). 80. 60. MOD1. (Theoretical curve assumes 0 dBFS input). 40. 20. Predictions for MOD2 are optimistic. Behavior of MOD1 is erratic. 0. 4 8 16 32 64 128 256 512 1024. ECE1371 1-37. Audio Demo: MOD1 vs. MOD2. Sine Wave MOD1. Slow Ramp MOD2. Speech ECE1371 1-38. MOD1 + MOD2 Summary ADCs rely on filtering and feedback to achieve high SNR despite coarse quantization They also rely on digital signal processing.


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