Layout of Analog CMOS Integrated Circuit - unipv

1 F. Maloberti - Layout of Analog cmos IC1F. MalobertiLayout of Analog CMOSI ntegrated CircuitPart 2 Transistors and Basic Cells LayoutF. Maloberti - Layout of Analog cmos IC2 Outline Introduction Process and Overview Topics Transistors and Basic Cells Layout Passive components: Resistors, Capacitors System level Mixed-signal LayoutF. Maloberti - Layout of Analog cmos IC3 Part II: Transistor and Basic Cell Layout Transistors and Matched Transistors Layout of a single transistor Use of multiple fingers Interdigitated devices Common Centroid Dummy devices on ends Matched interconnect (metal, vias, contacts) Surrounded by guard ring Design for Layout Stacked Layout of Analog cells Stick diagram of Analog cells Example 1: two stages op-amp Example 2: folded cascodeF. Maloberti - Layout of Analog cmos IC4 Single Transistor Layout A cmos transistor is the crossing of two rectangles,polysilicon and active area but, .. we need the drain and source connections and weneed to bias the substrate or the welldiffusionPolysilicon gateF.

2 Maloberti - Layout of Analog cmos IC5 Source and Drain Connections Ensure good connections Multiple contacts or one big contact?F. Maloberti - Layout of Analog cmos IC6 Multiple or single contacts? Curvature in the metal layer can lead to micro-fractures Not important for large areasReliability problems, possible electro-migrationF. Maloberti - Layout of Analog cmos IC7 Multiple contacts: Exercise Consider the following design rules: minimum contact spacing contact-contact minimum grid strep spacing contact diffusion Estimate the number of contacts and their spacing for W=50 W=52 W=60 F. Maloberti - Layout of Analog cmos IC8 Matching single Transistors Regular (rectangular shape) the W and L matter!! Parallel elements silicon is unisotropic Possibly, the current flowingin the same directionF. Maloberti - Layout of Analog cmos IC9 Asymmetry due to FabricationShadowed region7 An MOS transistor is not a symmetrical device. To avoid channeling ofimplanted ions the wafer is tilted by about 7.

3 Source and drain are not equivalentF. Maloberti - Layout of Analog cmos IC10 Parasitics in Transistors)2)(2(diffDdiffDBSBlLlWCC++== Analog transistors often have a large W/L ratio Capacitance diffusion substrateWLD Resistance of the poly gatepolysqgategateRLR,=F. Maloberti - Layout of Analog cmos IC11 Use of multiple fingersWSSSSDDDDDW/2W/3';21 DBDBDBSBCCCC==SBSBCC'32=DBDBCC'32=DBSBCC '';F. Maloberti - Layout of Analog cmos IC12 Parasitic in Transistors: Exercise Calculate the parasitic capacitance diffusion-substrate for a 40 micron width transistor one finger 5 finger 8 finger Use the design rules available and minimum diffusion lengthF. Maloberti - Layout of Analog cmos IC13 Interdigitated Devices Two matched transistors with one node in common spilt them in an equal part of fingers (for example 4) interdigitate the 8 elements: AABBAABB or ABBAABBAB2A31 AABBAABB213 ABBAABBA213F. Maloberti - Layout of Analog cmos IC14 Axis of SymmetriesABBAABABABA(A)(B)(C)Common axisof symmetryAxis of symmetryof device AAxis of symmetryof device BCommon axis ofsymmetryF.

4 Maloberti - Layout of Analog cmos IC15 Interdigitiation PatternsAAAAAAAAAAAB*ABBAABBAAB*ABABBABA ABC*ABCCBAABCBACBCA*ABCABCCBACBAABCD*ABC DDCBAABCBCADBCDA*ABCDDCBAABCDDCBAABAABAA BAABAABAABAABAABAABAABAABABAABABAABABAAB ABAABABAABABAABABAABABAABABAABABAAABA*AA BAABAAAABAAABAAABA*AABAABAAAABAABAAAABAA AABAAAABAAAABAAAABAAAABAAAABAAAABAAAABAA AABAANote: not all the patterns permit a stacked layoutF. Maloberti - Layout of Analog cmos IC16 Interdigitated Transistors: Exercises Sketch the Layout of two interdigitated transistorshaving W1=3W2 and split W2 into 4 fingers. M1 and M2have their source in common. Sketch the Layout of three interdigitized transistorshaving the same width. Use the optimum number offingers. The three transistors have the source Maloberti - Layout of Analog cmos IC17 Common CentroidDBDADADBDBDADADB Gradients in features are compensated for (at firstapproximation) metal and poly interconnections are more complexF. Maloberti - Layout of Analog cmos IC18 Common Centroid ArraysABBABBAAABBAC ross couplingTiling (more sensitive to high-order gradients)F.

5 Maloberti - Layout of Analog cmos IC19 Common Centroid PatternsABBAABBAABBAABBAABBAABBAABBABAAB BAABBAABBAABBAABBAABBAABABBAABBABAABBAAB ABBAABBAABAABAABAABAABAABAABAABABABBABBA BBABBABBABBABBABABAABABABBABBABABAABAABA ABCCBAABCCBAABCABCCBAABCABCCBAABCCBAABCC BAABCCBACBAABCCBACBAABCCBAABCCBAABCCBAAB CCBAABCCBAABCAABAABBAAAABBAAAABBAABAABAA AABBAAAABBAAAABAABBAABAAAABAABBAAF. Maloberti - Layout of Analog cmos IC20 Dummy Devices on Ends Ending elements have different boundary conditionsthan the inner elements -> use dummy Dummies are shorted transistors Remember their parasitic contribution!sbdF. Maloberti - Layout of Analog cmos IC21 Matched interconnections Specific resistance of metal lines Specific resistance of poly Resistance of metal-contact Resistance of viaIZVint= Minimize the interconnection impedance Achieve the same impedance in differential paths Keep short the width of fingers for high speed applicationsF. Maloberti - Layout of Analog cmos IC22 Matched Metal ConnectionF.

6 Maloberti - Layout of Analog cmos IC23 Waffle TransistorSDMinimum capacitancedrain-substrate andsource-substrateW not accurateL not well definedTo be used in wide transistorswhose aspect ratio is notrelevantF. Maloberti - Layout of Analog cmos IC24 Part II: Transistor and Basic Cell Layout Transistors and Matched Transistors Layout of a single transistor Use of multiple fingers Interdigitated devices Common Centroid Dummy devices on ends Matched interconnect (metal, vias, contacts) Surrounded by guard ring Design for Layout Stacked Layout of Analog cells Stick diagram of Analog cells Example 1: two stages op-amp Example 2: folded cascodeF. Maloberti - Layout of Analog cmos IC25 Stacked Layout Systematic use of stack or transistors (multi-fingerarrangement) Same width of the fingers in the same stack, possiblydifferent length Design procedure Examine the size of transistors in the cell Split transistors size in a number of Layout oriented fingers Identify the transistors that can be placed on the same stack Possibly change the size of non-critical transistors Use (almost) the same number of finger per stack place stacks and interconnectF.

7 Maloberti - Layout of Analog cmos IC26 Stick Representation (one transistor)sdsdssdsddsdsdsdsdEnding drainEnding sourceD/S endingS/D endingsdEVENODDF. Maloberti - Layout of Analog cmos IC27 Multi-transistor Stick Diagram1231234412342 Same widthM1M2M3M1 double1212323434M1M2M3343212343M3M2M1M2M 334322343M3M2M1M2M32113241F. Maloberti - Layout of Analog cmos IC28 Example 1 (2 stages OTA)M1M2M3M4M5M6M7606040303072108 Assume to Layout a two stages OTAW idth only are shown; Compensation network and bias are missing (!)F. Maloberti - Layout of Analog cmos IC29 Layout Oriented DesignM1M2M3M4M5M6M7606040303072108 Possible stacks:1 p-channel, 2 n-channelchange the size of M6 and M7 to 80 and 120 respectivelyWidth of each finger?We want the same number of fingers per stack (k).Wp1 = 180/kWn1=120/kWn2=120/kfor M3 and M4 use 2 fingersM3, M4, M6M1, M2M5, M7 Only width mattersF. Maloberti - Layout of Analog cmos IC30 Stack Design and InterconnectionsM1M2M3M4M5M6M76642288M6M 6M3M4M7M7M5 First attempt ofinterconnections(not completed)GNDOUTCSO1 VDDD3M1M2D3O1F.

8 Maloberti - Layout of Analog cmos IC31 Use of one Metal LayerM1M2M3M4M5M6M7 GNDOUTCSO1 VDDD3 GNDVDDM1 CSO1 OUTM2M4M3 Use metal for carrying current!Poly connections arenot a problem (usually)M5M5F. Maloberti - Layout of Analog cmos IC32 Stick Layout : ExerciseDraw the stick diagram of the two stages OTA in the following three cases: fingers of M6 and M7 all together M6 =90 M7=60 M1 and M2 in a common centroid arrangementF. Maloberti - Layout of Analog cmos IC33 From Stick to Layout Input-Output Well and its bias Substrate bias Compensation Bias voltage Bias currentVDDGND Rectangular shape System oriented cell Layout Related cells with same height Vdd and GND crossing the cell In and Out properly placedF. Maloberti - Layout of Analog cmos IC34 Example 2 (Folded Cascode)M1M2M3M4M11M5M7M9M6M8M1030308080 MN6060161638382525 Only Ws are shown20 MPF. Maloberti - Layout of Analog cmos IC35 Split of TransistorsM1M2M3M4M11M5M7M9M6M8M1030308 080MN606016164040242420233662538525332 MPF.

9 Maloberti - Layout of Analog cmos IC36 Stack DesignM1M2M3M4M11M5M7M9M6M8M10MN23366525 332MP10x2555555344PP33466666611221122112 21122112222112211221122112211777779xxoo9 9nno88888X=11; o=10F. Maloberti - Layout of Analog cmos IC37 Interconnection: ExerciseSketch the source-drain interconnections of the folded-cascodeF. Maloberti - Layout of Analog cmos IC38 Basic Cell Design: check-list Draw a well readable transistordiagram Identify critical elements andnodes Absolute and relative accuracy Minimum parasitic capacitance Minimum interference Mark transistors that mustmatch Mark symmetry axes Analyze transistor sizing (W s) Possibly, change transistor sizefor a Layout oriented strategy Group transistors in stacks Define the expected height(or width) of the cell Sketch the stick diagram transistors of the same type inthe same region Foresee room for substrateand well biasing substrate bias around the cell well-bias surrounding the well Define the connection layerfor input-output (horizontal,vertical connections) Begin the Layout now!

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