LECTURE 080 – ALL DIGITAL PHASE LOCK LOOPS (ADPLL)

1 LECTURE 080 All DIGITAL PPLs (5/15/03)Page 080-1 ECE 6440 - Frequency Synthesizers Allen - 2003 LECTURE 080 ALL DIGITAL PHASE LOCK LOOPS ( adpll )(Reference [2])Outline Building Blocks of the adpll Examples of adpll Implementation adpll Design adpll System SimulationLecture 080 All DIGITAL PPLs (5/15/03)Page 080-2 ECE 6440 - Frequency Synthesizers Allen - 2003 BUILDING BLOCKS OF THE ADPLLWhat is an All DIGITAL PLL? An adpll is a PLL implemented only by DIGITAL blocks The signal are DIGITAL (binary) and may be a single DIGITAL signal or a combination ofparallel DIGITAL Diagram of an ADPLLD igitalPhase DetectorDigitalLoopFilterDigitalVCOv1v2' "vd""vf"SquareWavesAdvantages: No off-chip components Insensitive to technologyLecture 080 All DIGITAL PPLs (5/15/03)Page 080-3 ECE 6440 - Frequency Synthesizers Allen - 2003 DIGITAL PHASE detectors WITH A PARALLEL OUTPUTAll of the PHASE detectors so far had only a 1-bit or analog Counter PDThis PHASE detector countsthe number of high-frequency clock periodsbetween the PHASE differenceof v1 and v2.

2 V1v2'tttt eQNContentFig. ClockN=content eFig. ' LECTURE 080 All DIGITAL PPLs (5/15/03)Page 080-4 ECE 6440 - Frequency Synthesizers Allen - 2003 Nyquist Rate PHASE DetectorUses an analog-to- DIGITAL 'v1v2'ClockDv1 ettt e etClockFig. canbe any digitizedwaveformLecture 080 All DIGITAL PPLs (5/15/03)Page 080-5 ECE 6440 - Frequency Synthesizers Allen - 2003 Zero-Crossing PHASE Detectorv1 AnalogDigitalConverterv1v2'ClockDv1 ett etClockFig. e' eSampledSampledSampledLecture 080 All DIGITAL PPLs (5/15/03)Page 080-6 ECE 6440 - Frequency Synthesizers Allen - 2003 Hilbert Transform PHASE DetectorThis PHASE detector uses the DIGITAL implementation of e = tan-1 cos ot cos( ot+ e) + sin ot sin( ot+ e) cos ot sin( ot+ e) + sin ot cos( ot+ e) - 2 DigitalMultiplierDigitalMultiplierDigita lMultiplierDigitalMultipliersin otcos otDigital VCOA dderAdderXYX/YDividercos esin etan etan-1 ev1(t)Hilbert PhaseTransformerv1(t) = cos( ot+ e)v1(t) = cos( ot+ e-90 ) = sin( ot+ e) Fig.

3 (t) LECTURE 080 All DIGITAL PPLs (5/15/03)Page 080-7 ECE 6440 - Frequency Synthesizers Allen - 2003 Hilbert Transform PHASE Detector ContinuedWaveforms:v1ttClockFig. 080 All DIGITAL PPLs (5/15/03)Page 080-8 ECE 6440 - Frequency Synthesizers Allen - 2003 DIGITAL -Averaging PHASE DetectorSimilar to the Hilbert transform but e and sin e are implemented by averaging (integrating) the output signals of themultipliers over an appropriate period of otcos otDigital VCOXYX/YDividercos esin etan etan-1 ev1(t)QIAveragerAveragerFig. PHASE detector includes a filter function defined by the impulse function of theaveraging 080 All DIGITAL PPLs (5/15/03)Page 080-9 ECE 6440 - Frequency Synthesizers Allen - 2003 LOOP FILTERS FOR THE ADPLLC ategories1.) PD s not having a parallel DIGITAL ) PD s having a parallel DIGITAL Counter Loop Filter The counter is an n-bitparallel output signal whichis the weighted sum of theUP and the DN pulses.

4 Thissignal approximates thefunction,H(s) = 1sTi whereTi = integrator timeconstantPulseFormingNetworkUPDNC lockUP/DNcontent N vfFromphasedetectorUP/DOWNC ounterClockUP/DNttUPDNtClocktUP/DNFig. 080 All DIGITAL PPLs (5/15/03)Page 080-10 ECE 6440 - Frequency Synthesizers Allen - 2003K Counter Loop Filter (74xx297)Works with EXOR or JK Flip-flop PDs. (fclock = Mfo)UP CounterDN CounterK clockDN/UPK modulus controlContents = 0, ,K-1,KCarryBorrow0 One cycle of v1tK clockM = 16tDN/UPtK/208UP CountertK/208DN Countert816 CarryBorrowtFig. counters count upwards. Carry = 1when contents of the UP counter = 1 when contents of the DN counter going edges of the Carry and Borrow control the 080 All DIGITAL PPLs (5/15/03)Page 080-11 ECE 6440 - Frequency Synthesizers Allen - 2003N before M Loop FilterBlock diagram:v1v2'PFD N Counter M Counter N CounterResetResetResetCarryBorrowReset to all countersUPDNFig.

5 >NOperation:The upper N counter will produce a carry pulse whenever more than N pulses of anensemble of M pulses have been UP lower N counter will produce a borrow pulse whenever more than N pulses ofan ensemble of M pulses have been DN performance of the filter is very 080 All DIGITAL PPLs (5/15/03)Page 080-12 ECE 6440 - Frequency Synthesizers Allen - 2003 DIGITAL Loop Filters with an N-bit Parallel Input SignalH(s) = O(s)I(s) If I(s) is L [ (t)], then O(s) = H(s)I(s) = H(s) = Impulse responseConvolution:h*(t) = T n=0 h(n) (t-nT) Frequency Domain:H*(s) = T n=0 h(n)e-nT z-Domain:H (z) = H*(s) |z=esT = T n=0 h(n)z-n Infinite Impulse Response (IIR) Filters-n Finite Impulse Response (FIR) Filters-n = NLecture 080 All DIGITAL PPLs (5/15/03)Page 080-13 ECE 6440 - Frequency Synthesizers Allen - 2003 FIR ExampleN = 31, no windowingN = 31, Hanning windowOther windows.

6 Hamming,Bartlett, Blackman, Kaiser, 0-10-20-30-40-50-60-70-80dB0 0 -20 -40 -60 -80-100-120dB0 LECTURE 080 All DIGITAL PPLs (5/15/03)Page 080-14 ECE 6440 - Frequency Synthesizers Allen - 2003 DIGITAL CONTROLLED OSCILLATORS N Counter N CounterN moduluscontrolFromloopfilterFixed high-frequencyoscillatorThe N-bit output signal of a DIGITAL loop filter is used to control the scaling factor N of the N 080 All DIGITAL PPLs (5/15/03)Page 080-15 ECE 6440 - Frequency Synthesizers Allen - 2003 Increment-Decrement CounterUsed with loop filters such as the K counter or N before M that output CARRY orBORROW clockCARRYBORROWOUTIDout = IDclock Toggle-FFa.) No BORROW or CARRY toggle-FF switches on everypositive edge of the ID clock if noCARRY or BORROW pulses ) CARRY input applied when the toggle-FF is in the low the toggle-FF goes high on thenext positive edge of the ID clock butstays low for the next two clockintervals, the IDout is advanced by oneID clock clockToggle FFIDoutFig.

7 ClockToggle FFID outtCARRYA dvancedFig. 080 All DIGITAL PPLs (5/15/03)Page 080-16 ECE 6440 - Frequency Synthesizers Allen - 2003 Increment-Decrement Counter Continuedc.) CARRY input applied when the toggle-FF is in the high toggle-FF is set low for the nexttwo clock the CARRY can only beprocessed when the toggle-FF is in the high-state, the maximum frequency of the IDoutsignal is reached when the toggle-FFfollows the pattern of high-low-low-high-low-low .Therefore, the maximum IDout frequency =2/3 ID clock frequency. This will limit the hold range of the ADPLLd.) Application of a BORROW BORROW pulse causes the toggle-FF to be set high on the suceeding twopositive edges of the ID causes the next IDout pulse to bedelayed by one ID clock period. Thetoggle-FF has the pattern of low-high-high-low-high-high which gives the frequency = 1/3 ID clock , 1 CARRY pulse adds 1/2 cycle and 1 BORROW pulse removes 1/2 clockToggle FFID outtCARRYA dvancedFig.

8 ClockToggle FFID outtBORROWD elayedFig. 080 All DIGITAL PPLs (5/15/03)Page 080-17 ECE 6440 - Frequency Synthesizers Allen - 2003 Waveform Synthesizer DCOP robably more suitable for software 080 All DIGITAL PPLs (5/15/03)Page 080-18 ECE 6440 - Frequency Synthesizers Allen - 2003 EXAMPLES OF adpll IMPLEMENTATIONE xample 1vdv1 DQCPFF1 QCPQM onostableFlip-FlopPulse Forming Circuitv1*JQKFF2 QDQCPFF3 CPUP/DN CounterUP/DNVariable NCounterTC MCounterTCCPv2 ResetLoadModulusControlN vfLoopFilterfcDigital Controlled OscillatorStartClockPhaseDetectorFig. :1.) Pulse forming circuit Downscales f1 by two to get v1*. v1 and v1* generate theclock for the loop filter. The negative-going edge of v1* generates a start ) DIGITAL controlled oscillator The variable N counter is a down counter. Its contentstarts with the number N loaded in parallel from the loop filter.

9 The clock, fc, causes thecounter to count down to 0. The content of the N counter at this time is called theterminal count (TC). The output pulse at TC reloads the content N in the N counter andstarts the M counter counting up from 0. When the M counter reaches TC, a pulse isdelivered at the output which is 080 All DIGITAL PPLs (5/15/03)Page 080-19 ECE 6440 - Frequency Synthesizers Allen - 2003 Example 1 ContinuedWhen the loop is locked, fc = MNf1. Note that the duration of the start pulse < 1 :Case 1 Early : N is too ) M counter reaches TC ) v2 causes the loop filter toincrease ) This process continues until the M counter reaches TC at thepositive edge of v1*.Case 2 Late : N is too ) M counter reaches TC after ) Under this condition, v2 causesthe loop filter to decrease ) This process continues until the M counter reaches TC at thepositive edge of v1*.

10 Tv1tv1*tCKtToToStartCase 1: "Early"tContent of M countertTCvdResetResetCase 2: "Late"tContent of M counterTC tvdSetSetFig. StateIndeterminant StateLecture 080 All DIGITAL PPLs (5/15/03)Page 080-20 ECE 6440 - Frequency Synthesizers Allen - 2003 Example 2 Uses the 74xx297v2v1v2'K counterID counterG1 JQKFFQDECINCLoopFilterEXOR Detector74xx297K modulus controlID clock2 NfoN Control N counterMfoK clockDN/UPEXOR outCPIDoutCARRYBORROWFig. lock, the average number of carry pulses and borrow pulses are equal and nocycles are added or deleted. If f1 increases, the output of the EXOR detector becomesasymmetrical in order to allow the K counter to produce more carry pulses than borrowpulses on 080 All DIGITAL PPLs (5/15/03)Page 080-21 ECE 6440 - Frequency Synthesizers Allen - 2003 Example 2 EXOR PD, M=16, K=4, and N=8 Assumptions: Loop is in lock Both counters counton the negative edgesof the K clock The toggle flip-flopwithin the ID countertoggles on thepositive edge of theID clock All flip-flops of the N counter count onthe negative edge ofthe correspondingclock signalNote that v2 has a 50%duty cycle which meansthat it has no ripple orphase ' (IDout 8)t0816K clock (Mfo)tttEXORout = DN/UPt4K/20 KUPt4K/20 KDNtCARRYtBORROWA dvancedAdvancedDelayedDelayedtID clock (2 Nfo)ttIDoutToggle FFtIDout 2tIDout 4 Fig.