Lecture 6: Logical Effort

1 Lecture 6: Logical Effort6: Logical Effort2 CMOS vlsi DesignCMOS vlsi Design 4th Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary6: Logical Effort3 CMOS vlsi DesignCMOS vlsi Design 4th Chip designers face a bewildering array of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? Logical Effort is a method to make these decisions Uses a simple model of delay Allows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries? ? ?6: Logical Effort4 CMOS vlsi DesignCMOS vlsi Design 4th Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. Decoder specifications: 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors Ben needs to decide: How many stages to use?

2 How large should each gate be? How fast can decoder operate?A[3:0] A[3:0]1632 bits16 words4:16 DecoderRegister File6: Logical Effort5 CMOS vlsi DesignCMOS vlsi Design 4th in a Logic Gate Express delays in process-independent unit Delay has two components: d = f+ p f: Effort delay = gh( stage Effort ) Again has two components g: Logical Effort Measures relative ability of gate to deliver current g 1 for inverter h: electrical Effort = Cout/ Cin Ratio of output to input capacitance Sometimes called fanout p: parasitic delay Represents delay of gate driving no load Set by internal parasitic capacitanceabsdd = =3RC 3 ps in 65 nm process60 ps in m process6: Logical Effort6 CMOS vlsi DesignCMOS vlsi Design 4th Effort :h = Cout/ CinNormalized Delay: dInverter2-inputNANDg = 1p = 1d = h + 1g = 4/3p = 2d = (4/3)h + 2 Effort Delay: fParasitic Delay: p0123450123456 Electrical Effort :h = Cout/ CinNormalized Delay: dInverter2-inputNANDg = p = d = g = p = d = 0123450123456 Delay Plotsd= f+ p= gh+ p What about NOR2?

3 6: Logical Effort7 CMOS vlsi DesignCMOS vlsi Design 4th Logical Effort DEF: Logical Effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. Measure from delay vs. fanout plots Or estimate by counting transistor widthsAYABYABY1211222244 Cin = 3g = 3/3 Cin = 4g = 4/3 Cin = 5g = 5/36: Logical Effort8 CMOS vlsi DesignCMOS vlsi Design 4th of Gates8, 16, 16, 86, 12, 64, 4 XOR, XNOR22222 Tristate / mux(2n+1)/39/37/35/3 NOR(n+2)/36/35/34/3 NAND1 Invertern4321 Number of inputsGate type Logical Effort of common gates6: Logical Effort9 CMOS vlsi DesignCMOS vlsi Design 4th of Gates864 XOR, XNOR2n8642 Tristate / muxn432 NORn432 NAND1 Invertern4321 Number of inputsGate type Parasitic delay of common gates In multiples of pinv( 1)6: Logical Effort10 CMOS vlsi DesignCMOS vlsi Design 4th : Ring Oscillator Estimate the frequency of an N-stage ring oscillatorLogical Effort : g = 1 Electrical Effort : h = 1 Parasitic Delay: p = 1 Stage Delay:d = 2 Frequency:fosc= 1/(2*N*d) = 1/4N31 stage ring oscillator in m process has frequency of ~ 200 MHz6: Logical Effort11 CMOS vlsi DesignCMOS vlsi Design 4th.

4 FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverterLogical Effort : g = 1 Electrical Effort : h = 4 Parasitic Delay: p = 1 Stage Delay:d = 5dThe FO4 delay is about300 ps in m process15 ps in a 65 nm process6: Logical Effort12 CMOS vlsi DesignCMOS vlsi Design 4th Logic Networks Logical Effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path EffortiGg= out-pathin-pathCHC=iiiFfgh== 10xyz20g1 = 1h1 = x/10g2 = 5/3h2 = y /xg3 = 4/3h3 = z /yg4 = 1h4 = 20/z6: Logical Effort13 CMOS vlsi DesignCMOS vlsi Design 4th Logic Networks Logical Effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort Can we write F = GH?iGg= out pathin pathCHC =iiiFfgh== 6: Logical Effort14 CMOS vlsi DesignCMOS vlsi Design 4th that Branch No! Consider paths that branch:G = 1H = 90 / 5 = 18GH = 18h1= (15 +15) / 5 = 6h2= 90 / 15 = 6F = g1g2h1h2= 36 = 2GH5151590906: Logical Effort15 CMOS vlsi DesignCMOS vlsi Design 4th Effort Introduce branching Effort Accounts for branching between stages in path Now we compute the path Effort F = GBHon pathoff pathon pathCCbC+=iBb= ihBH= Note:6: Logical Effort16 CMOS vlsi DesignCMOS vlsi Design 4th Delays Path Effort Delay Path Parasitic Delay Path DelayFiDf= iPp= iFDdDP==+ 6: Logical Effort17 CMOS vlsi DesignCMOS vlsi Design 4th Fast Circuits Delay is smallest when each stage bears same Effort Thus minimum delay of N stage path is This is a keyresult of Logical Effort Find fastest possible delay Doesn t require calculating gate sizesiFDdDP==+ 1 Niifgh F==1 NDNF P=+6: Logical Effort18 CMOS vlsi DesignCMOS vlsi Design 4th Sizes How wide should the gates be for least delay?

5 Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives. Check work by verifying input cap spec is met. outiniiCCioutinfghggCCf== =6: Logical Effort19 CMOS vlsi DesignCMOS vlsi Design 4th : 3-stage path Select gate sizes x and y for least delay from A to B8xxxyy4545AB6: Logical Effort20 CMOS vlsi DesignCMOS vlsi Design 4th : 3-stage pathLogical EffortG = (4/3)*(5/3)*(5/3) = 100/27 Electrical EffortH = 45/8 Branching EffortB = 3 * 2 = 6 Path EffortF = GBH = 125 Best Stage EffortParasitic DelayP = 2 + 3 + 2 = 7 DelayD = 3*5 + 7 = 22 = FO48xxxyy4545AB3 5fF==6: Logical Effort21 CMOS vlsi DesignCMOS vlsi Design 4th : 3-stage path Work backward for sizesy = 45 * (5/3) / 5 = 15x = (15*2) * (5/3) / 5 = 10P: 4N: 44545 ABP: 4N: 6P: 12N: 38xxxyy4545AB6: Logical Effort22 CMOS vlsi DesignCMOS vlsi Design 4th Number of Stages How many stages should a path use? Minimizing number of stages is not always fastest Example: drive 64-bit datapath with unit inverterD = NF1/N+ P= N(64)1/N + DriverDatapath LoadN:f: : Logical Effort23 CMOS vlsi DesignCMOS vlsi Design 4th Consider adding inverters to end of path How many give least delay?

6 Define best stage Effort N - n1 Ex t r a In v er t er sLogic Block:n1 StagesPa t h Ef f o r t F()1111 NniinviDNFp Nnp==++ 111ln0 NNNinvDFFFpN = + + = ()1ln0invp + =1NF =6: Logical Effort24 CMOS vlsi DesignCMOS vlsi Design 4th Stage Effort has no closed-form solution Neglecting parasitics (pinv= 0), we find = (e) For pinv= 1, solve numerically for = ()1ln0invp + =6: Logical Effort25 CMOS vlsi DesignCMOS vlsi Design 4th Analysis How sensitive is delay to using exactly the best number of stages? < < 6 gives delay within 15% of optimal We can be sloppy! I like = ( = )( =6)D(N) /D(N) : Logical Effort26 CMOS vlsi DesignCMOS vlsi Design 4th , Revisited Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. Decoder specifications: 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors Ben needs to decide: How many stages to use?

7 How large should each gate be? How fast can decoder operate?A[3:0] A[3:0]1632 bits16 words4:16 DecoderRegister File6: Logical Effort27 CMOS vlsi DesignCMOS vlsi Design 4th of Stages Decoder Effort is mainly electrical and branchingElectrical Effort :H = (32*3) / 10 = Effort :B = 8 If we neglect Logical Effort (assume G = 1)Path Effort :F = GBH = of Stages:N = log4F = Try a 3-stage design6: Logical Effort28 CMOS vlsi DesignCMOS vlsi Design 4th Sizes & DelayLogical Effort :G = 1 * 6/3 * 1 = 2 Path Effort :F = GBH = 154 Stage Effort :Path Delay:Gate sizes:z = 96*1 18 y = 18*2 [3]A[3]A[2] A[2]A[1] A[1]A[0] A[0]word[0]word[15]96 units of wordline capacitance1010101010101010yzyz1/3 31 4 1 +++=6: Logical Effort29 CMOS vlsi DesignCMOS vlsi Design 4th Compare many alternatives with a spreadsheet D = N( G)1/N+ : Logical Effort30 CMOS vlsi DesignCMOS vlsi Design 4th of Definitionsdelayparasitic delayeffort delayeffortbranching effortelectrical effortlogical effortnumber of stagesPathStageTermiGg= out-pathin-pathCCH=NiBb= FGBH=FiDf= iPp= iFDdDP==+ outinCCh=on-pathoff-pathon-pathCCCb+=fgh =fpdfp=+g16: Logical Effort31 CMOS vlsi DesignCMOS vlsi Design 4th of Logical Effort1) Compute path effort2) Estimate best number of stages3) Sketch path with N stages4) Estimate least delay5) Determine best stage effort6) Find gate sizesFGBH=4logNF=1 NDNF P=+1 NfF= iiioutingCCf=6: Logical Effort32 CMOS vlsi DesignCMOS vlsi Design 4th of Logical Effort Chicken and egg problem Need path to compute G But don t know number of stages without G Simplistic delay model Neglects input rise time effects Interconnect Iteration required in designs with wire Maximum speed only Not minimum area/power for constrained delay6.

8 Logical Effort33 CMOS vlsi DesignCMOS vlsi Design 4th Logical Effort is useful for thinking of delay in circuits Numeric Logical Effort characterizes gates NANDs are faster than NORs in CMOS Paths are fastest when Effort delays are ~4 Path delay is weakly sensitive to stages, sizes But using fewer stages doesn t mean faster paths Delay of path is about log4F FO4 inverter delays Inverters and NAND2 best for driving large caps Provides language for discussing fast circuits But requires practice to master