Low Drop-Out (LDO) Linear Regulators: Design ...

1 IEEE Santa Clara Valley (SCV). Solid State Circuits Society February 11, 2110. Low Drop-Out (LDO) Linear regulators : Design Considerations and Trends for high Power- Supply Rejection (PSR). Edgar S nchez-Sinencio TI J. Kilby Chair Professor Analog and Mixed-Signal Center, Texas A&M University 1. Power Management Why do we need power management? Batteries discharge almost linearly with time. To optimize the charging of batteries to be safe and extend their life. Circuits with reduced power supply that are time dependent operate poorly. Optimal circuit performance can not be obtained. Mobile applications impose saving power as much as possible. Thus, the sleep mode and full power mode must be carefully controlled. Objective of a power converter is to provide a regulated output voltage Voltage Battery ( Li-ion). Regulated Voltage Time 2. What are the conventional power converters? Low drop out Linear regulator (LDO). Switch inductor regulator (switching regulators ). Switch capacitor regulator (charge pump).

2 Why do we need different Power Converters Types? Different applications Desired efficiency and output ripple Can we combine them? +. Battery SR LDO VREGULATED. - +. Battery CP LDO VREGULATED. - +. Battery LDO CP VREGULATED. - What is the purpose of combining several converters? 3. Linear Regulator: Basic Idea +. RC Vo must be constant and R << R. C LOAD. RLOAD VO. VBAT VBAT is changing as a function of time - RLOAD. VO = VBAT. RLOAD + RC. Thus in order to keep constant Vo, the value of the controlling resistor RC yields: V V V V . R =R. C LOAD.. BAT. 1 = R LOAD. BAT O. = R LOAD.. LDO.. V. O V O V . O. So RC should be controlled such that Vo= Vdesired, reg voltage RC. +. VC. Feedback RLOAD VO. VBAT. Control - 4. Low Dropout Voltage Regulator (LDO). The LDO act as a variable resistor that is placed between input power source and the load in order to drop and control the voltage applied to the load. Compared to DC DC switching regulators , LDOs are: Of continuous operation Easier to use Vin Cheaper solution Iin But of Lower efficiency LDO.

3 EA. P V I V V V Control RC. OUT = OUT LOAD < OUT = IN LDO Circuit Vout Iout PIN VIN I IN VIN VIN. VLDO. 1 . VBAT Rload The output error voltage (EVO) is defined as: R V V. E 100% C. OR E = OUT MAX OUT LOAD. 100%. R +R. VO VO. C LOAD. V OUT MAX. 5. Implementing RC and the Feedback Control NMOS Pass Transistor PMOS Pass Transistor VGS. a b a b a b VC = VGS ILOAD VC = -VGS = VSG. VDO,n= VSAT+Vgs VDO = ILOADRC VDO,p= VSD(SAT). VO. VO. R1 Error Amplifier R1. Error Amplifier VC,NMOS VC,PMOS. R2 R2. VREF VREF. For an ideal op amp gain, the differential input is zero, R R . V V 2. 0 OR V =V = V = 1 + 1. V. R +R. O UT REG O REF. R . O REF. 1 2 2. VREF is a Bandgap voltage which is also supplied by VBAT=VIN. 6. LDO Analysis Let us analyze the basic LDO architecture. First, we will consider ideal components, then the non idealities are introduced together with the accompanied Design challenges to tackle. BG is the band gap reference voltage. VIN. Error Amplifier BG VX gm( Vx ViN ) rop PMOS Pass Transistor VIN =.

4 VBAT AEA VIN AEA( VDIV - VREF) Vo R1 R1. VDIV Io VDIV RL. R2 Load (RL) R2. Basic LDO Topology Small Signal Representation 1 1 1 1 1 .. VO + + VIN + g m VDIV + g m AEA = g m AEAVREF. (1). rop RL R1 rop R1 . 1 1 V. VDIV + O = 0 (2). R1 R2 R1. 7. Solving the (1) and (2), Vo becomes: Vin (1 + APT ) + V REF APT AEA . Vo =. rop [1 + APT AEA + ]. RL. Where: APT = g m rop , = R2 /( R1 + R2 ), and ( R1 + R2 ) >> R L. Thus Vo can be expressed as: Vin APT V A A . Vo = + REF PT EA. (1 + APT AEA ) (1 + APT AEA ). Vin T / AEA V T. If T = APT AEA Vo yields: Vo + REF. (1 + T ) (1 + T ). T is the open loop gain. Furthermore for T >>1. Vin V. Vo + REF. AEA . Observe that Vin is attenuated by AEA and Vref is not. 8. Line Regulation The line regulation is a steady-state specification. It can be defined as: Vo APT APT. LR = = =. Vin (1 + APT AEA ) 1 + APT AEA. V 1. L = . o V A. R. in EA. For a practical case with non-idealities such as offset Op-Amp voltage Vos and reference voltage error Vref ; the line regulator becomes: Vo 1 R V + Vos.

5 = + 1 + 1 REF . Vin AEA R2 Vin . Observe that designers should also minimize: Vos and provide Vref to be independent of VBAT and temperature and process variations. 9. Issues of Concern in LDO Design Error Amplifier VREF. Bandgap Mp : PMOS Pass Transistor VIN = VBAT. Vout AError_Amp ZL. Rf1. Io VDIV. Load (RL) CL. Rf2. Pass transistor load current will determine its size and thus layout Error amplifier The accuracy required by the LDO, determines the magnitude of the open loop gain. Single pole architectures are recommended for better and easier stability. The amp transient requirement is dependent on the stability gain and phase margins. There is a trade off in making the PM high and speed of amp. This is also true for the Gain. Should have high PSRR. Bandgap voltage reference Should have high PSR. Stability and speed of the feedback loop Should be assured under all load conditions Choice of the capacitors and feedback resistors (Rf1 and Rf2). 10. NMOS vs. PMOS Pass Transistor NMOS pass FET is easier to compensate at low loads and dropout, due to the higher output impedance of PMOS.

6 NMOS pass FET are smaller due to weaker drive of PMOS. NMOS pass FET LDO requires the VDD rail to be higher than Vin, while a PMOS does not. To do this, a charge pump is usually required with accompanying disadvantages of higher quiescent current and extra charge pump noise. Power Supply Rejection (PSR) is better with PMOS. 11. LDO Significant Parameters 1. Dropout voltage (Vdo): This is the difference between the minimum voltage the input DC supply can attain and the regulated output voltage. Input rail range: This is the input supply voltage range that can be regulated. Lower limit is dependent on the dropout voltage and upper limit depends on the process capability. Output regulated voltage range: This is the output voltage variation the regulator guarantees. When output voltage is in this range, it is said to be in regulation. Vout Dropout voltage = X - Y. Output Y. regulated range ~1. Input rail range X. Vin 12. LDO Significant Parameters 1. Output current range: This is the output current handling capability of the regulated output voltage.

7 Minimum current limit is mainly dependent on the stability requirements Maximum current limit is dependent on Safe Operating Area (SOA) of pass FET and also maintaining output voltage in regulation. Load regulation: This is the variation in output voltage as current moves from min. to max. Line regulation: This is the variation in output voltage as supply voltage is varied from min. to Load/Line transient regulation: This is a measure of the response speed of the regulator when subjected to a fast load/Vsupply change. IL Load transient regulation Vin Line transient regulation IL_max Vin_max Vin_min IL_min t t Vout Vout t t 13. LDO Significant Parameters 2. PSR: Power Supply Rejection (or ripple rejection) is a measure of the ac coupling between the input supply voltage on the output voltage. Power Efficiency; This is the ratio of the output load power consumption to input supply power. Linear regulators are not really efficient especially at high input supply voltages.

8 Output capacitor range: This is the specified output capacitance the regulator is expected to accommodate without going unstable for a given load current range. Short circuit current limit: This is the current drawn when the output voltage is short circuited to ground. The lower limit is determined by the maximum regulated load current and the upper limit is mainly determined by the SOA. and specified requirements. Overshoot; It is important to minimized high transient voltages at start up and during load and line transients. 14. high PSR using Feed Forward Ripple Cancellation Technique References. M. El Nozahi, A. Amer, J. Torres, K. Entesari, and E. S nchez Sinencio, A 25mA m CMOS LDO Regulator with Power Supply Rejection better than 56dB up to 10 MHz using Feed Forward Ripple Rejection Technique, . in Proceeding of IEEE International Solid State Circuits Conference, Feb. 2009. M. El Nozahi, A. Amer, J. Torres, K. Entesari, and E. S nchez Sinencio, LDO with Feed forward Ripple Cancellation Technique for high Power Supply Rejection, to appear in J.

9 Of Solid State Circuits, Mar. 2010. 15. Motivation Power Management System Switching LDO Vsupply Battery converter Regulator Battery Analog / RF / Digital Charger Circuit Blocks Problem: Supply ripples affect Analog/RF blocks Switching converter ripple frequencies are increasing Solution: LDO with good PSR at higher operating frequencies Challenges: Low drop out voltage, low quiescent current, small area, high PSR across a wide frequency range 16. Introduction Conventional LDO. Input Output Ripples Paths Low frequency: Bandgap (VREF) and Error Amplifier high frequency: Pass transistor and loop GBW. 17. Prior Work Existing Techniques: RC filtering Cascading LDOs Combined RC and cascading Increasing Loop Bandwidth Drawbacks: Large area consumption Large dropout voltage high power consumption ) All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies 18. Proposed Architecture: Feed Forward Ripple Cancellation (FFRC) LDO. Main Idea: Cancellation path replicates the ripples at gate of pass transistor Gate source overdrive voltage is free of ripples 19.

10 Mathematical Model of FFRC LDO. _. + gds Pass Transistor Load VIN + +. + R L (1 + sR ESR C L ). gm VOUT. _ 1 + sR L C L. A sum 1 + s / p _ sum Summing Amplifier Error Amplifier + + A err R2. HFF(s). 1+ s / p _ err R 2 + R1. Feed-forward amplifier Optimum HFF(s) for a zero transfer gain: Asum gm H FF ( s ) =1. 1+ s / p _ sum g m + g ds 20. Circuit Implementation 21. Main Features high Power Supply Rejection Low drop out Voltage: same as conventional LDOs Loop Dynamics: same as conventional LDOs Error Amplifier: specifications are relaxed compared to conventional LDOs Low power consumption Low sensitivity to process Variation: ratio of resistors 22. PCB View of the LDO. Capacitor ESL and the trace inductance limit the performance at higher frequencies The traces and the bonding wires should be modeled during the simulations 23. Chip Die Photo Technology: UMC m CMOS 24. PSR Measurement Results 25. PSR Degradation PSR degrades at higher frequencies due to: Finite GBW of feed forward amplifier (cancellation path).