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M. Morris Mano DIGITAL DESIGN, - Computer Science

Combinational n inputs m outputs circuit .. Fig. 4-1 Block Diagram of Combinational Circuit 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. A T2. B. C F1. A T1. B. C. T3. F 2. A. B. A. F2. C. B. C. Fig. 4-2 Logic Diagram for Analysis Example 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. CD C CD C. AB 00 01 11 10 AB 00 01 11 10. 00 1 1 00 1 1. 01 1 1 01 1 1. B B. 11 X X X X 11 X X X X. A A. 10 1 X X 10 1 X X. D D. z D y CD C D . CD C CD C. AB 00 01 11 10 AB 00 01 11 10. 00 1 1 1 00. 01 1 01 1 1 1 B. B. 11 X X X X 11 X X X X. A A. 10 1 X X 10 1 1 X X. D D. X B C B D BC D w A BC BD. 2002 Prentice Hall, Inc. M.

Fig. 4-2 Logic Diagram for Analysis Example A B A B C A B C A C B C F 2 F 1 T 3 T 2 T 1 F 2 © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

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Transcription of M. Morris Mano DIGITAL DESIGN, - Computer Science

1 Combinational n inputs m outputs circuit .. Fig. 4-1 Block Diagram of Combinational Circuit 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. A T2. B. C F1. A T1. B. C. T3. F 2. A. B. A. F2. C. B. C. Fig. 4-2 Logic Diagram for Analysis Example 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. CD C CD C. AB 00 01 11 10 AB 00 01 11 10. 00 1 1 00 1 1. 01 1 1 01 1 1. B B. 11 X X X X 11 X X X X. A A. 10 1 X X 10 1 X X. D D. z D y CD C D . CD C CD C. AB 00 01 11 10 AB 00 01 11 10. 00 1 1 1 00. 01 1 01 1 1 1 B. B. 11 X X X X 11 X X X X. A A. 10 1 X X 10 1 1 X X. D D. X B C B D BC D w A BC BD. 2002 Prentice Hall, Inc. M.

2 Morris Mano Fig. 4-3 Maps for BCD to Excess-3 Code Converter DIGITAL design , 3e. D z D CD y C. (C D) . C D. B. x w A. Fig. 4-4 Logic Diagram for BCD to Excess-3 Code Converter 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. x y . S. x x S. y y x C C. y (a) S xy x y (b) S x y C xy C xy Fig. 4-5 Implementation of Half-Adder 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. yz y yz y 00 01 11 10 00 01 11 10. x x 0 1 1 0 1. x 1 1 1 x 1 1 1 1. z z S x y z x yz xy z xyz S xy xz yz xy xy z x yz Fig. 4-6 Maps for Full Adder 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. x . y . z x y x . y z . x S C. z x y.

3 Z . y z x y z Fig. 4-7 Implementation of Full Adder in Sum of Products 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. x y S. C. z Fig. 4-8 Implementation of Full Adder with Two Half Adders and an OR Gate 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. B3 A3 B2 A2 B1 A1 B0 A0. C3 C2 C1. FA FA FA FA C0. C4 S3 S2 S1 S0. Fig. 4-9 4-Bit Adder 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. Ai Pi Bi Si Gi Ci 1. Ci Fig. 4-10 Full Adder with P and G Shown 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. C3. P2. G2. C2. P1. G1. P0 C1. G0. C0. Fig. 4-11 Logic Diagram of Carry Lookahead Generator 2002 Prentice Hall, Inc.

4 M. Morris Mano DIGITAL design , 3e. C4 C4. B3. P3. A3. P3. S3. C3. G3. B2. P2. A2 P2. S2. C2. G2. Carry Look ahead B1 generator P1. A1 P1. S1. C1. G1. B0. P0. A0 P0. S0. G0. C0 C0. 2002 Prentice Hall, Inc. Fig. 4-12 4-Bit Adder with Carry Lookahead M. Morris Mano DIGITAL design , 3e. B3 A3 B2 A2 B1 A1 B0 A0. M. C4 C3 C2 C1 C0. C FA FA FA FA. S3 S2 S1 S0. V. Fig. 4-13 4-Bit Adder Subtractor 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. Addend Augend Carry Carry K 4- bit binary adder out in Z8 Z4 Z2 Z1. Output carry 0. 4- bit binary adder S8 S4 S2 S1. 2002 Prentice Hall, Inc. M. Morris Mano Fig. 4-14 Block Diagram of a BCD Adder DIGITAL design , 3e.

5 B1 B0 A0. B1 B0. A1 A0. A0B1 A 0B 0. A1B1 A1B0. A1. C3 C2 C1 C0 B1 B0. HA HA. C3 C2 C1 C0. Fig. 4-15 2-Bit by 2-Bit Binary Multiplier 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. A0. B3 B2 B1 B0. A1. B3 B2 B1 B0. 0. Addend Augend 4-bit adder Sum and output carry A2. B3 B2 B1 B0. Addend Augend 4-bit adder Sum and output carry C6 C5 C4 C3 C2 C1 C0. 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. Fig. 4-16 4-Bit by 3-Bit Binary Multiplier A3. x3. B3. A2. x2. B2. (A B). A1. x1. B1. A0. x0 (A B). B0. (A B). 2002 Prentice Hall, Inc. Fig. 4-17 4-Bit Magnitude Comparator M. Morris Mano DIGITAL design , 3e. D 0 x y z.

6 D 1 x y z z D 2 x yz . y D 3 x yz D 4 xy z . x D 5 xy z D 6 xyz . D 7 xyz 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. Fig. 4-18 3-to-8-Line Decoder D0. E A B D0 D1 D2 D3. D1. 1 X X 1 1 1 1. A 0 0 0 0 1 1 1. 0 0 1 1 0 1 1. D2 0 1 0 1 1 0 1. B 0 1 1 1 1 1 0. D3. E. (a) Logic diagram (b) Truth table Fig. 4-19 2-to-4-Line Decoder with Enable Input 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. x 3 8. y D 0 to D 7. decoder z E. w 3 8. D 8 to D 15. decoder E. Fig. 4-20 4 16 Decoder Constructed with Two 3 8 Decoders 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. 0. 1. S. x 22 2. 3 8 3. y 21 decoder 4.

7 Z 20 5 C. 6. 7. Fig. 4-21 Implementation of a Full Adder with a Decoder 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. D2 D2. 00 01 11 10 00 01 11 10. 00 X 1 1 1 00 X 1 1 1. 01 1 1 1 01 1 1 1 1. D1 D1. 11 1 1 1 11 1 1 1 1. D0 D0. 10 1 1 1 10 1 1 1. D3 D3. x D2 D 3 y D3 D1D 2. Fig. 4-22 Maps for a Priority Encoder 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. D3. y D2. D1. x V. D0. Fig. 4-23 4-Input Priority Encoder 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. I0. I0 0. Y MUX Y. I1 1. I1. S. S. (a) Logic diagram (b) Block diagram Fig. 4-24 2-to-1-Line Multiplexer 2002 Prentice Hall, Inc. M.

8 Morris Mano DIGITAL design , 3e. I0 s1 s0 Y. 0 0 I0. 0 1 I1. I1 1 0 I2. 1 1 I3. Y. I2 (b) Function table I3. s1. s0. (a) Logic diagram 2002 Prentice Hall, Inc. Fig. 4-25 4-to-1-Line Multiplexer M. Morris Mano DIGITAL design , 3e. A0. Y0. A1. Y1. A2. Y2. A3. Y3. B0. Function table E S Output Y. B1. 1 X all 0's 0 0 select A. B2 0 1 select B. B3. S. (select). E. (enable). 2002 Prentice Hall, Inc. Fig. 4-26 Quadruple 2-to-1-Line Multiplexer M. Morris Mano DIGITAL design , 3e. 4 1 MUX. y S0. x S1. x y z F. 0 0 0 0. 0 0 1 1 F z z 0 F. 0 1 0 1. F z z 1. 0 1 1 0. 1 0 0 0 0 2. F 0. 1 0 1 0. 1 3. 1 1 0 1. F 1. 1 1 1 1. (a) Truth table (b) Multiplexer implementation Fig.

9 4-27 Implementing a Boolean Function with a Multiplexer 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. 8 1 MUX. A B C D F. C S0. 0 0 0 0 0. 0 0 0 1 1 F D B S1. 0 0 1 0 0 A S2. F D. 0 0 1 1 1. 0 1 0 0 1 D. F D 0. 0 1 0 1 0. 1. 0 1 1 0 0 F. 0 1 1 1 0 F 0 2. 1 0 0 0 0 0 3. F 0. 1 0 0 1 0 4. 1 0 1 0 0. F D 5. 1 0 1 1 1. 1 1 0 0 1 1 6. F 1. 1 1 0 1 1 7. 1 1 1 0 1. F 1. 1 1 1 1 1. Fig. 4-28 Implementing a 4-Input Function with a Multiplexer 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. Normal input A Output Y A if C 1. High impedance if C 0. Control input C. Fig. 4-29 Graphic Symbol for a Three-State Buffer 2002 Prentice Hall, Inc.

10 M. Morris Mano DIGITAL design , 3e. I0 Y. I1. I2. A Y I3. 0. S1. Select 1. B S0 2 4. decoder 2. Enable EN. Select 3. (a) 2-to-1- line mux (b) 4 - to - 1 line mux Fig. 4-30 Multiplexers with Three-State Gates 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. in out in out control control bufifl bufif0. in out in out control control notifl notif0. Fig. 4-31 Three-State Gates 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. A out B. select Fig. 4-32 2-to-1-Line Multiplexer with Three-State Buffers 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL design , 3e. Stimulus module design module module testcircuit module circuit (A, B, C).


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